Motorola MC68030 User Manual page 253

Bus Operation
CLK
+5
VOLTS
V CC
RESET
BUS
CYCLES
BUS STATE UNKNOWN
Resetting the processor causes any bus cycle in progress to terminate as if DSACKx,
BERR, or STERM had been asserted. In addition, the processor initializes registers
appropriately for a reset exception. Exception processing for a reset operation is described
in 8.1.1 Reset Exception.
When a reset instruction is executed, the processor drives the RESET signal for 512 clock
cycles. In this case, the processor resets the external devices of the system, and the internal
registers of the processor are unaffected. The external devices connected to the RESET
signal are reset at the completion of the reset instruction. An external RESET signal that is
asserted to the processor during execution of a reset instruction must extend beyond the
reset period of the instruction by at least eight clock cycles to reset the processor. Figure 7-
65 shows the timing information for the reset instruction.
7-107
Figure 7-64. Initial Reset Operation Timing
MC68030 USER'S MANUAL
t = >520 CLOCKS
1<4 CLOCKS
ENTIRE ALL CONTROL SIGNALS
BUS HIGH INACTIVE. DATA BUS IN
IMPEDANCE READ MODE. ADDRESS
4 CLOCKS
ISP
BUS DRIVEN
READ
STARTS
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