Synchronous Read-Modify-Write Cycle - Motorola MC68030 User Manual

Bus Operation
State 3
The processor negates AS (and DS, if necessary) during S3. It holds the address and data
valid during S3 to simplify memory interfaces. R/W, SIZ0–SIZ1, FC0–FC2, and DBEN
also remain valid throughout S3.
The addressed device must negate STERM within two clock periods after asserting it, or
the processor may use STERM for the next bus cycle.

7.3.6 Synchronous Read-Modify-Write Cycle

A synchronous read-modify-write operation differs from an asynchronous read-modify-write
operation only in the terminating signal of the read and write cycles and in the use of CLK
instead of DS latching data in the write cycle. Like the asynchronous operation, the
synchronous read-modify-write operation is indivisible. Although the operation is
synchronous, the burst mode is never used during read-modify-write cycles.
Figure 7-35 is a flowchart of the synchronous read-modify-write operation. Timing for the
cycle is shown in Figure 7-36.
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