Processing System Clock Source - Xilinx ZC702 User Manual

• LVDS Differential Output
The user clock circuit is shown in
X-Ref Target - Figure 1-12
VCC3V3
USRCLK SDA
USR CLK SCL
The Silicon Labs Si570 data sheet is available on the Silicon Labs website

Processing System Clock Source

[Figure 1-2, callout 8]
The Processing System (PS) clock source is a 1.8V LVCMOS single-ended fixed
33.33333 MHz oscillator at U65. It is wired to PS bank 500, pin F7 (PS_CLK), on the XC7Z020
AP SoC.
• Oscillator: SiTime SiT8103AC-23-18E-33.33333 (33.3 MHz)
• Frequency jitter: 50 ppm
• Single-ended output
For more details, see the SiTime SiT8103 data sheet
The system clock circuit is shown in
ZC702 Board User Guide
UG850 (v1.2) April 4, 2013
Figure
U28
R20
Si570
4.7KΩ 5%
Programmable
Oscillator
1
NC VDD
2
OE
7
SDA
CLK-
8
SCL CLK+
3
GND
GND
Figure 1-12: User Clock Source
Figure
www.xilinx.com
1-12.
VCC3V3
C216
0.01 µF 25V
X7R
6
GND
USRCLK N
R417
5
100Ω 1%
4 USRCLK P
UG850_c1_12_030513
[Ref 5].
1-13.
Feature Descriptions
[Ref 6].
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