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CPU MultiProcessor Test Group

These tests are launched at Power-On and are also available under the control of the Off
Line Tests monitor. These tests check the multi-processor mechanisms, atomic instructions,
cache coherency, main memory sharing, and multi-resources sharing.
The following tests are available under this group.
Atomic Instructions Test
This test checks the mechanisms enabling the protection of the content of the memory in
case of use of some specific instructions, called "atomic instructions".
Cache Coherency Test
This test is performed by two processors on the same CPU card. It checks the capability of a
CPU card to manage all the H/W systems, maintaining the coherency between all the
caches. This test checks the following H/W parts:
1. CPU processors (partially)
4. L2 cache
This test is made of 9 sub-tests, which are launched on two processors, Processor 0 and
Processor 1. Processor 1 is often used to verify the operation started by Processor 0. These
two processors concurrently access the same memory area, with various access modes
enabled. The following is a brief description of the various sub-tests. Suitable error
messages are generated by each test, whenever an error is detected.
Concurrent Coherent Write Access-Copy Back
Concurrent Not Coherent Write Access-Copy Back
Concurrent Coherent Write Access-DCBST from Line Owner
Concurrent Coherent Write Access-DCBF from Line Owner
Concurrent Coherent Write Access-DCBI from Line Owner
Operator Guide
In this test, both the processors are enabled in Global Copy Back
mode. The snoop mechanism is activated to ensure cache
coherency. Processor 0, writes a half word in memory (actually,
data is in Processor 0 cache). Then Processor 1 writes another half
word in memory (actually, data is in Processor 1 cache). When
Processor 1 is writing, Processor 0 cache updates memory. When
Processor 0 tries to read the full word, Processor 1 cache is erased.
This test puts both the processors in Local Copy Back Mode. Each
processor does a write-read operation.
The global snoop mechanism is not enabled in this test and the
caches are not coherent. So when Processor 0 is reading memory,
Processor 1 cache is not erased.
This test verifies the DCBST(update memory) instruction from the
Processor 0. Processor 0 is set to Global Write Through mode and
caching is enabled. The odd processor is uncached without
In this test, Processor 0 is enabled for Write through and Memory
coherency parameters. Processor 0 issues a DCBF (Data Cache
Block Flush) instruction. Processor 1 cache is inhibited and memory
coherency is absent.
This test verifies the DCBI (Data Cache Block Invalidate)


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