BPP External LoopBack Test (BPP EXT L–B TEST
Note: This test can only be performed by Field or Manufacturing people.
This test checks the accessibility of the Super–IO chip. It saves and restores used registers.
This test is not performed at power on.
JTAG Test Group
These tests check the chip to chip connections using the JTAG features. These tests are run
automatically by the BUMP.
The following three tests are available under this group:
Nodes Detection Test
This test detects all the connections between the chips. These detected nodes can be
stored on a Floppy diskette and loaded to NVRAM under the Maintenance menu, as soon as
a JTAG test is to be performed.
This test uses the JTAG capabilities to read or set the pins of the chips. This test builds a
node which is made up of set of pins which are linked, or pins which are not linked to a
node but directly linked to Vcc or GND (pull-up or pull-down). The nodes are stored in the
This test processes all the nodes of the "nodes" file, in order to check the integrity of the
links between the chips. This test checks if an error is present but doesn't localize the errors.
When an error is detected, the test stops and the error is reported.
This test checks all the nodes of the "nodes" file, looking for any differences between what is
read via JTAG and what has been memorized in the "nodes" file. If an error is detected, it is
stored in the "faults" file. This test is slow but it localizes the problems.
When JTAG tests are selected under the Off Line Test Control, the JTAG Test Monitor menu
is displayed. This menu performs the following main functions,
Test Execution: Execution of the preceding tests in Normal or Trace mode (step by step).
Display Nodes files / Faults Files: It is possible to view the entire nodes file / faults file.
Display Configuration File: To view the h/w specific information (like the input pins,
Tri-stated pins, number of boards, etc).
More information about JTAG tests is awaited.
Direct I/O Test Group
These tests are performed by all processors at Power-On and are under control of the Off
Line Test monitor. These tests check the accessibility of the Standard and Direct I/O
components from the CPUs. The following tests are available under this group.
Sub test #
Possible Values Default Value
0 or 1
0 = All tests linked
8 = BUMP