Dcb And Memory Test Group - IBM R30 Operator's Manual

Level 2 Cache Data Test
TAG Data Test
Walking 1 TAG Test
Walking 0 TAG Test
Mini-Addressing TAG Test
EEPROM Compatibility Test
This test is done primarily to check the compatibility of the EEPROM contents (VPD code)
with the actual status of the machine. This results in checking of the information coherency.
This test contains the following sub-test:
EEPROM Compatibility Test

DCB and Memory Test Group

All of these tests except the Memory Components Test, in this group are performed by all of
the processors. The tests are launched at Power-On and under the control of the Off Line
Test Monitor. This test group checks the status of the System Planar and Memory cards.
The following tests are available in this group.
Data Lines Accessibility Test
This test checks the accessibility for all the data lines to the memory, through DCB ASICs.
The following h/w parts are checked by running this test.
1. DCB ASICs
2. SMC ASIC (partially)
3. Connection of data lines between CPU cards and System Planar ASICs
4. Connection of data lines between System Planar ASICs and memory chips.
This test consists of four sub-tests. Words manipulated / used are not restored at the end of
the test. This test applies to one of the four memory cards. The following is a description of
the sub-tests.
Work Area Test
A-12
Operator Guide
in memory and in cache. Then it reads the second MB from cache
and first MB from the memory.
This test checks the validity of the static memory RAMs forming the
Level 2 cache. It calculates the memory address available and then
validates the Level 2 cache before writing 1 MB. Then a read
operation is done in word mode and values are compared. Then a
read is done in burst mode and comparison is done.
This test checks the availability of the TAG chips of the L2 cache
memory.
This test verifies data integrity.
This test verifies data integrity.
This test checks L2 cache addresses.
During this test, BUMP reads the CPU card VPD and puts the
information in the parameter area. The processor then reads the
PVR register and compares the parameter values with the PVR
register values.
The 2 values are available in the temporary test result area, in
NVRAM.
This sub-test is used to find a working area which is safe enough to
perform other sub-tests. It first calculates the memory location and
0s are written on the first long word and verified. Then 1s are written
and verified. If the verification is OK, the sub-test is ended and the
next sub-test is started.