IBM R30 Operator's Manual page 224

Main Memory Components Test
This test is performed by all the processors to check all the main memory locations. From
the h/w point of view, this test checks the memory chips mounted on the main memory
cards. This test can be launched in two modes, as follows:
1. Bit Map Elaboration Mode: This is at Power On and performed with execution mode
parameter set to 0.
2. Localization Mode: This is possible in the maintenance menu, under the control of
Off Line Test Monitor. It is performed on a selected area with the execution mode
parameter set to 1.
This test has two sub-tests, as follows:
Address in to Address Memory Test
Complemented Address in to Address Memory Test
A-16
Operator Guide
This test is done in two phases.
In the Write phase, the first address to be written is calculated and
the BAT is initialized. Then the last address to be written in the 1MB
block, is found and the writing loop is begun. This loop writes the
address of the location as the data in to the memory location, and
after each write operation the address is incremented. This loop
continues until the working address is equal to the end address. If it
is equal, Read and Compare phase begins.
In the Read and Compare phase, the first address to be read and
compared is found and BATs initialization is done. Then the last
address to read and compare in the 1MB block is calculated. Now,
the Read and Compare loop is begun where each memory location
is read and compared with the theoretical value. In case of no
errors, the loop ends when all the locations have been verified. If an
error is detected, a console message giving the details of the error
is displayed.
This test is conducted in the same manner as the previous test
except that, the location address is complemented and written.