of slave frequency inverter with address 02 H. Then the structure of this frame
is described as follows:
RTU host machine order information
START
Slave machine address
Command code
Write data address high-order
Write data address low-order
Data content high-order
Data content low-order
CRC CHK low-order
CRC CHK high-order
END
RTU Slave machine responding information(normal)
START
Slave machine address
Command code
Write data address high-order
Write data address low-order
Data content high-order
Data content low-order
CRC CHK low-order
CRC CHK high-order
END
RTU Slave machine responding information(abnormal)
START
Slave machine address
Command code
Error code
CRC CHK low-order
CRC CHK high-order
Transmission time of 3.5 bytes
02H
06H
01H
10H
13H
88H
84H
96H
Transmission time of 3.5 bytes
Transmission time of 3.5 bytes
02H
06H
01H
10H
13H
88H
84H
96H
Transmission time of 3.5 bytes
Transmission time of 3.5 bytes
02H
86H
01H
73H
A0H
179