NEC 78K0S/KB1+ User Manual page 228

(3) External interrupt mode register 0 (INTM0)
This register is used to set the valid edge of INTP0 to INTP2.
INTM0 is set with an 8-bit memory manipulation instruction.
Reset signal generation clears INTM0 to 00H.
Figure 13-4. Format of External Interrupt Mode Register 0 (INTM0)
Address: FFECH After reset: 00H
Symbol 7 6
INTM0 ES21 ES20
ES21 ES20
0 0
0 1
1 0
1 1
ES11 ES10
0 0
0 1
1 0
1 1
ES01 ES00
0 0
0 1
1 0
1 1
Cautions 1. Be sure to clear bits 0 and 1 to 0.
2. Before setting the INTM0 register, be sure to set the corresponding interrupt mask flag
(××MK× = 1) to disable interrupts. After setting the INTM0 register, clear the interrupt
request flag (××IF× = 0), then clear the interrupt mask flag (××MK× = 0), which will
enable interrupts.
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CHAPTER 13 INTERRUPT FUNCTIONS
R/W
5 4 3
ES11 ES10 ES01
Falling edge
Rising edge
Setting prohibited
Both rising and falling edges
Falling edge
Rising edge
Setting prohibited
Both rising and falling edges
Falling edge
Rising edge
Setting prohibited
Both rising and falling edges
User's Manual U17446EJ3V1UD
2 1 0
ES00 0 0
INTP2 valid edge selection
INTP1 valid edge selection
INTP0 valid edge selection