NEC 78K0S/KB1+ User Manual page 113

f
XP
2
f /2
XP
8
f /2
XP
Noise
TI000/INTP0/P30
eliminator
f
XP
Count clock
TM00 count value
CR000 capture value
CR010 capture value
Remark 0000H < M < N ≤ FFFFH
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-30. Configuration Diagram of PPG Output
16-bit timer capture/compare
register 000 (CR000)
16-bit timer counter 00
16-bit timer capture/compare
register 010 (CR010)
Figure 6-31. PPG Output Operation Timing
t
0000H 0001H
N
Clear
TO00
Pulse width: (M + 1) × t
1 cycle: (N + 1) × t
User's Manual U17446EJ3V1UD
(TM00)
M − 1
N − 1
M
N
Clear
N
M
Clear
circuit
TO00/TI010/
INTP2/P31
0000H 0001H
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