NEC 78K0S/KB1+ User Manual page 240

(b) Release by reset signal generation
When the reset signal is generated, HALT mode is released, and then, as in the case with a normal reset
operation, the program is executed after branching to the reset vector address.
Figure 14-3. HALT Mode Release by Reset Signal Generation
(1) When CPU clock is high-speed internal oscillation clock or external input clock
Reset signal
CPU status
System clock
oscillation
Note Operation is stopped (277
referenced.
Reset signal
CPU status
System clock
oscillation
Note Operation is stopped (276
referenced.
Remark f : System clock oscillation frequency
X
Table 14-3. Operation in Response to Interrupt Request in HALT Mode
Release Source
Maskable interrupt request
Reset signal generation
×: don't care
240
CHAPTER 14 STANDBY FUNCTION
HALT
instruction
Operation
HALT mode
mode
Oscillates
μ
s (MIN.), 544
(2) When CPU clock is crystal/ceramic oscillation clock
HALT
instruction
Operation
HALT mode
mode
Oscillates
μ
s (MIN.), 544
MK××
0
0
1
−
User's Manual U17446EJ3V1UD
Operation
Reset
Note
stops
period
Oscillation stops
μ
s (TYP.), 1.075 ms (MAX.)) because the option byte is
Oscillation
Operation
Reset
Note
stabilization waits
stops
period
Oscillation stops
Oscillation stabilization time
10
(2
μ
s (TYP.), 1.074 ms (MAX.)) because the option byte is
IE Operation
0 Next address instruction execution
1 Interrupt servicing execution
×
HALT mode held
×
Reset processing
Operation mode
Oscillates
Operation
mode
Oscillates
17
/f to 2 /f )
X X