NEC 78K0S/KB1+ User Manual page 112

Figure 6-29. Control Register Settings for PPG Output Operation
7 6
CRC00 0 0
7 OSPT00 OSPE00
TOC00 0 0
ES110 ES100 ES010
PRM00 0/1 0/1
7 6
TMC00 0 0
Cautions 1. Values in the following range should be set in CR000 and CR010.
0000H < CR010 < CR000 ≤ FFFFH
2. The cycle of the pulse generated through PPG output (CR000 setting value + 1) has a duty of
(CR010 setting value + 1)/(CR000 setting value + 1).
Remark ×: Don't care
112
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
(a) Capture/compare control register 00 (CRC00)
5 4 3 CRC002 CRC001
×
0 0 0 0
(b) 16-bit timer output control register 00 (TOC00)
TOC004 LVS00 LVR00 TOC001
0 1 0/1 0/1 1
(c) Prescaler mode register 00 (PRM00)
ES000 3 2 PRM001
0/1 0/1 0 0 0/1
(d) 16-bit timer mode control register 00 (TMC00)
5 4 TMC003 TMC002 TMC001
0 0 1 1 0
User's Manual U17446EJ3V1UD
CRC000
0
CR000 used as compare register
CR010 used as compare register
TOE00
1
Enables TO00 output.
Inverts output on match between TM00 and CR000.
Specifies initial value of TO00 output F/F (setting "11" is prohibited).
Inverts output on match between TM00 and CR010.
Disables one-shot pulse output.
PRM000
0/1
Selects count clock.
Setting invalid (setting "10" is prohibited.)
Setting invalid (setting "10" is prohibited.)
OVF00
0
Clears and starts on match between TM00 and CR000.