NEC 78K0S/KB1+ User Manual page 124

(18) Edge detection
<1> In the following cases, note with caution that the valid edge of the TI0n0 pin is detected.
(a) Immediately after a system reset, if a high level is input to the TI0n0 pin, the operation of the 16-bit
timer counter 00 (TM00) is enabled
→ If the rising edge or both rising and falling edges are specified as the valid edge of the TI0n0 pin,
a rising edge is detected immediately after the TM00 operation is enabled.
(b) If the TM00 operation is stopped while the TI0n0 pin is high level, TM00 operation is then enabled
after a low level is input to the TI0n0 pin
→ If the falling edge or both rising and falling edges are specified as the valid edge of the TI0n0 pin,
a falling edge is detected immediately after the TM00 operation is enabled.
(c) If the TM00 operation is stopped while the TI0n0 pin is low level, TM00 operation is then enabled
after a high level is input to the TI0n0 pin
→ If the rising edge or both rising and falling edges are specified as the valid edge, of the TI0n0 pin,
a rising edge is detected immediately after the TM00 operation is enabled.
Remark n = 0, 1
<2> The sampling clock used to remove noise differs when a TI000 valid edge is used as the count clock and
when it is used as a capture trigger. In the former case, the count clock is f
count clock is selected by prescaler mode register 00 (PRM00). The capture operation is not performed
until the valid edge is sampled and the valid level is detected twice, thus eliminating, noise with a short
pulse width.
(19) External event counter
<1> The timing of the count start is after two valid edge detections.
<2> When reading the external event counter count value, TM00 should be read.
(20) PPG output
<1> Values in the following range should be set in CR000 and CR010:
0000H < CR010 < CR000 ≤ FFFFH
<2> The cycle of the pulse generated through PPG output (CR000 setting value + 1) has a duty of (CR010
setting value + 1)/(CR000 setting value + 1).
(21) STOP mode or system clock stop mode setting
Except when the valid edge of the TI000 pin is selected as the count clock, stop the timer operation before
setting STOP mode or system clock stop mode; otherwise the timer may malfunction when the system clock
starts.
(22) P31/TI010/TO00 pin
When using P31 as the input pin (TI010) of the valid edge, it cannot be used as a timer output pin (TO00).
When using P31 as the timer output pin (TO00), it cannot be used as the input pin (TI010) of the valid edge.
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
User's Manual U17446EJ3V1UD
, and in the latter case the
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