NEC 78K0S/KB1+ User Manual page 397

Function Details of
Function
Standby Settings and
function operating
statuses in HALT
mode
Settings and
operating
statuses in STOP
mode
−
Reset
function
Timing of reset
by overflow of
watchdog timer
RESF: Reset
control flag
register
Power-on- Functions of
clear circuit power-on-clear
circuit
Cautions for
power-on-clear
circuit
Low- LVIM: Low-
voltage voltage detect
detector register
LVIS: Low-
voltage detection
level select
register
When used as
reset
APPENDIX D LIST OF CAUTIONS
Because an interrupt request signal is used to clear the standby mode, if there
is an interrupt source with the interrupt request flag set and the interrupt mask
flag reset, the standby mode is immediately cleared if set.
Because an interrupt request signal is used to clear the standby mode, if there
is an interrupt source with the interrupt request flag set and the interrupt mask
flag reset, the standby mode is immediately cleared if set. Thus, in the STOP
mode, the normal operation mode is restored after the STOP instruction is
executed and then the operation is stopped for 34
additional wait time for stabilizing the oscillation set by the oscillation
stabilization time select register (OSTS) has elapsed when crystal/ceramic
oscillation is used).
For an external reset, input a low level for 2
During reset signal generation, the system clock and low-speed internal
oscillation clock stop oscillating.
When the RESET pin is used as an input-only port pin (P34), the 78K0S/KB1+
is reset if a low level is input to the RESET pin after reset is released by the
POC circuit and before the option byte is referenced again. The reset status is
retained until a high level is input to the RESET pin.
The LVI circuit is not reset by the internal reset signal of the LVI circuit.
The watchdog timer is also reset in the case of an internal reset of the
watchdog timer.
Do not read data by a 1-bit memory manipulation instruction.
If an internal reset signal is generated in the POC circuit, the reset control flag
register (RESF) is cleared to 00H.
Because the detection voltage (V
±0.1 V, use a voltage in the range of 2.2 to 5.5 V.
In a system where the supply voltage (V
the vicinity of the POC detection voltage (V
repeatedly reset and released from the reset status. In this case, the time
from release of reset to the start of the operation of the microcontroller can be
arbitrarily set by taking the following action.
To stop LVI, follow either of the procedures below.
• When using 8-bit manipulation instruction: Write 00H to LVIM.
• When using 1-bit memory manipulation instruction: Clear LVION to 0.
Be sure to set bits 2 to 6 to 0.
Bits 4 to 7 must be set to 0.
If values other than same values are written during LVI operation, the value
becomes undefined at the very moment it is written, and thus be sure to stop
LVI (bit 7 of LVIM register (LVION) = 0) before writing.
<1> must always be executed. When LVIMK = 0, an interrupt may occur
immediately after the processing in <3>.
) ≥ detection voltage (V
If supply voltage (V
DD
internal reset signal is not generated.
User's Manual U17446EJ3V1UD
Cautions
μ
s (TYP.) (after an
μ
s or more to the RESET pin.
) of the POC circuit is in a range of 2.1 V
POC
) fluctuates for a certain period in
DD
), the system may be
POC
) when LVIM is set to 1, an
LVI
(15/19)
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