NEC 78K0S/KB1+ User Manual page 247

<1> With high-speed internal oscillation clock or external clock input
High-speed internal oscillation clock or
external clock input
CPU clock
RESET
Internal reset signal
Port pin
(except P130)
Port pin
(P130)
Notes 1. The operation stop time is 277
2. Set high level output using software.
Remark When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is
effected, the output signal of P130 can be dummy-output as the reset signal to the CPU.
Crystal/ceramic
oscillation clock
Normal operation
RESET
Internal reset signal
Port pin
(except P130)
Port pin
(P130)
Notes 1. The operation stop time is 276
2. Set high level output using software.
Remarks 1. f : System clock oscillation frequency
X
2. When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is
effected, the output signal of P130 can be dummy-output as the reset signal to the CPU.
CHAPTER 15 RESET FUNCTION
Figure 15-2. Timing of Reset by RESET Input
Normal operation
in progress
Delay
100 ns (TYP.)
μ
s (MIN.), 544
<2> With crystal/ceramic oscillation clock
Reset period
(oscillation stops)
in progress
Delay
100 ns (TYP.)
μ
s (MIN.), 544
User's Manual U17446EJ3V1UD
Reset period
Normal operation (reset processing, CPU clock)
(oscillation stops)
Operation stops because option
byte is referenced
Delay
100 ns (TYP.)
Hi-Z
μ
s (TYP.), and 1.075 ms (MAX.).
Oscillation stabilization
10 17
time (2 /f to 2 /f )
X X
Operation stops because option
byte is referenced
Delay
100 ns (TYP.)
Hi-Z
μ
s (TYP.), and 1.074 ms (MAX.).
Note 1
.
Note 2
Normal operation
(reset processing, CPU clock)
Note 1
.
Note 2
247