Examples Of Internal Verify Operation In Self Programming Mode - NEC 78K0S/KB1+ User Manual

19.8.9 Examples of internal verify operation in self programming mode

Examples of internal verify 1 and 2 operations in self programming mode are explained below.
• Internal verify 1
<R>
<1> Set 01H (internal verify 1) to the flash program command register (FLCMD).
<2> Set the block number for which internal verify is performed, to flash address pointer H (FLAPH).
<3> Set 00H to the flash address pointer L (FLAPL).
<4> Write the same value as that of FLAPH to the flash address pointer H compare register (FLAPHC).
<5> Set FFH to the flash address pointer L compare register (FLAPLC).
<6> Clear the flash status register (PFS).
<7> Write ACH to the watchdog timer enable register (WDTE) (clear and restart the watchdog timer counter)
<8> Execute the HALT instruction then start self programming. (Execute an instruction immediately after the
HALT instruction if self programming has been executed.)
<9> Check if a self programming error has occurred using bit 1 (VCERR) and bit 2 (WEPRERR) of PFS.
Abnormal → <10>
→ <11>
Normal
<10> Internal verify processing is terminated abnormally.
<11> Internal verify processing is terminated normally.
• Internal verify 2
<R>
<1> Set 02H (internal verify 2) to the flash program command register (FLCMD).
<2> Set the block number for which internal verify is performed, to flash address pointer H (FLAPH).
<3> Set the verify start address to the flash address pointer L (FLAPL).
<4> Write the same value as that of FLAPH to the flash address pointer H compare register (FLAPHC).
<5> Set the verify end address to the flash address pointer L compare register (FLAPLC).
<6> Clear the flash status register (PFS).
<7> Write ACH to the watchdog timer enable register (WDTE) (clear and restart the watchdog timer counter)
<8> Execute the HALT instruction then start self programming. (Execute an instruction immediately after the
HALT instruction if self programming has been executed.)
<9> Check if a self programming error has occurred using bit 1 (VCERR) and bit 2 (WEPRERR) of PFS.
Abnormal → <10>
→ <11>
Normal
<10> Internal verify processing is terminated abnormally.
<11> Internal verify processing is terminated normally.
Note This setting is not required when the watchdog timer is not used.
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