NEC 78K0S/KB1+ User Manual page 95

Cautions 1. Always set data to PRM00 after stopping the timer operation.
2. If the valid edge of the TI000 pin is to be set as the count clock, do not set the clear/start
mode and the capture trigger at the valid edge of the TI000 pin.
3. In the following cases, note with caution that the valid edge of the TI0n0 pin is detected.
<1> Immediately after a system reset, if a high level is input to the TI0n0 pin, the
operation of the 16-bit timer counter 00 (TM00) is enabled
→ If the rising edge or both rising and falling edges are specified as the valid edge
<2> If the TM00 operation is stopped while the TI0n0 pin is high level, TM00 operation is
then enabled after a low level is input to the TI0n0 pin
→ If the falling edge or both rising and falling edges are specified as the valid edge
<3> If the TM00 operation is stopped while the TI0n0 pin is low level, TM00 operation is
then enabled after a high level is input to the TI0n0 pin
→ If the rising edge or both rising and falling edges are specified as the valid edge
4. The sampling clock used to eliminate noise differs when a TI000 valid edge is used as the
count clock and when it is used as a capture trigger. In the former case, the count clock
is f , and in the latter case the count clock is selected by prescaler mode register 00
XP
(PRM00). The capture operation is not performed until the valid edge is sampled and the
valid level is detected twice, thus eliminating noise with a short pulse width.
5. When using P31 as the input pin (TI010) of the valid edge, it cannot be used as a timer
output pin (TO00). When using P31 as the timer output pin (TO00), it cannot be used as
the input pin (TI010) of the valid edge.
Remark n = 0, 1
(5) Port mode register 3 (PM3)
This register sets port 3 input/output in 1-bit units.
When using the P31/TO00/TI010/INTP2 pin for timer output, set PM31 and the output latch of P31 to 0.
When using the P30/TI000/INTP0 and P31/TO00/TI010/INTP2 pins as a timer input, set PM30 and PM31 to 1.
At this time, the output latches of P30 and P31 can be either 0 or 1.
PM3 is set by a 1-bit or 8-bit memory manipulation instruction.
Generation of reset signal sets the value of PM3 to FFH.
Address: FF23H
Symbol
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
of the TI0n0 pin, a rising edge is detected immediately after the TM00 operation is
enabled.
of the TI0n0 pin, a falling edge is detected immediately after the TM00 operation is
enabled.
of the TI0n0 pin, a rising edge is detected immediately after the TM00 operation is
enabled.
Figure 6-9. Format of Port Mode Register 3 (PM3)
After reset: FFH
7 6 5
PM3 1 1 1
PM3n P3n pin I/O mode selection (n = 0 to 3)
0 Output mode (output buffer on)
1 Input mode (output buffer off)
User's Manual U17446EJ3V1UD
R/W
4 3 2 1 0
1 PM33 PM32 PM31 PM30
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