NEC 78K0S/KB1+ User Manual page 84

Figure 5-14. Status Transition of Low-Speed Internal Oscillation
Clock source of
WDT is selected
by software
LSRSTOP = 1
Note The clock source of the watchdog timer (WDT) is selected from f
refer to CHAPTER 9 WATCHDOG TIMER.
84
CHAPTER 5 CLOCK GENERATORS
Select by option byte
if low-speed internal oscillator
can be stopped or not
Can be stopped
Note
Low-speed internal
oscillator can be stopped
LSRSTOP = 0
Low-speed internal
oscillator stops
User's Manual U17446EJ3V1UD
Power
application
> 2.1 V ±0.1 V
V
DD
Reset by
power-on-clear
Cannot be stopped
Low-speed internal
oscillator cannot be stopped
or f
X RL
Reset signal
Clock source of
WDT is fixed to f
RL
, or it may be stopped. For details,