NEC 78K0S/KB1+ User Manual page 88

• When CR000 is used as a capture register
It is possible to select the valid edge of the TI000 pin or the TI010 pin as the capture trigger. Setting of the
TI000 or TI010 valid edge is performed by means of prescaler mode register 00 (PRM00) (refer to Table 6-
2).
Table 6-2. CR000 Capture Trigger and Valid Edges of TI000 and TI010 Pins
(1) TI000 pin valid edge selected as capture trigger (CRC001 = 1, CRC000 = 1)
CR000 Capture Trigger
Falling edge
Rising edge
No capture operation
(2) TI010 pin valid edge selected as capture trigger (CRC001 = 0, CRC000 = 1)
CR000 Capture Trigger
Falling edge
Rising edge
Both rising and falling edges
Remarks 1. Setting ES010, ES000 = 1, 0 and ES110, ES100 = 1, 0 is prohibited.
2. ES010, ES000:
ES110, ES100:
CRC001, CRC000: Bits 1 and 0 of capture/compare control register 00 (CRC00)
Cautions 1. Set CR000 to other than 0000H in the clear & start mode entered on match between TM00
and CR000.
register is used as an external event counter. However, in the free-running mode and in
the clear & start mode using the valid edge of TI000 pin, if CR000 is set to 0000H, an
interrupt request (INTTM000) is generated when CR000 changes from 0000H to 0001H
following overflow (FFFFH).
2. If the new value of CR000 is less than the value of 16-bit timer counter 0 (TM00), TM00
continues counting, overflows, and then starts counting from 0 again. If the new value of
CR000 is less than the old value, therefore, the timer must be reset to be restarted after
the value of CR000 is changed.
3. The value of CR000 after 16-bit timer/event counter 00 has stopped is not guaranteed.
4. The capture operation may not be performed for CR000 set in compare mode even if a
capture trigger is input.
5. When using P31 as the input pin (TI010) of the valid edge, it cannot be used as a timer
output pin (TO00). When using P31 as the timer output pin (TO00), it cannot be used as
the input pin (TI010) of the valid edge.
6. If the register read period and the input of the capture trigger conflict when CR000 is
used as a capture register, the capture trigger input takes precedence and the read data
is undefined. Also, if the count stop of the timer and the input of the capture trigger
conflict, the capture trigger is undefined.
88
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Rising edge
Falling edge
Both rising and falling edges
Falling edge
Rising edge
Both rising and falling edges
Bits 5 and 4 of prescaler mode register 00 (PRM00)
Bits 7 and 6 of prescaler mode register 00 (PRM00)
This means a 1-pulse count operation cannot be performed when this
User's Manual U17446EJ3V1UD
TI000 Pin Valid Edge
ES010
0
0
1
TI010 Pin Valid Edge
ES110
0
0
1
ES000
1
0
1
ES100
0
1
1