NEC 78K0S/KB1+ User Manual page 388

Function Details of
Function
16-bit One-shot pulse
timer/event output with
counter 00 external trigger
Timer start errors
One-shot pulse
output
Capture
operation
Changing
compare register
during timer
operation
External event
counter
External clock
limitation
8-bit timer CR80: 8-bit
80 compare register
80
TMC80: 8-bit
timer mode
control register
80
388
APPENDIX D LIST OF CAUTIONS
Do not input the external trigger again while the one-shot pulse is being
output. To output the one-shot pulse again, wait until the current one-shot
pulse output is completed.
Do not set 0000H to the CR000 and CR010 registers.
16-bit timer counter 00 starts operating as soon as a value other than 0, 0
(operation stop mode) is set to the TMC002 and TMC003 bits.
An error of up to one clock may occur in the time required for a match signal to
be generated after timer start. This is because 16-bit timer counter 00 (TM00)
is started asynchronously to the count clock.
One-shot pulse output normally operates only in the free-running mode or in
the clear & start mode at the valid edge of the TI000 pin. Because an overflow
does not occur in the clear & start mode on a match between TM00 and
CR000, one-shot pulse output is not possible.
If both the rising and falling edges are selected as the valid edges of the TI000
pin, capture is not performed.
When the CRC001 bit value is 1, the TM00 count value is not captured in the
CR000 register when a valid edge of the TI010 pin is detected, but the input
from the TI010 pin can be used as an external interrupt source because
INTTM000 is generated at that timing.
With the 16-bit timer capture/compare register 0n0 (CR0n0) used as a
compare register, when changing CR0n0 around the timing of a match
between 16-bit timer counter 00 (TM00) and 16-bit timer capture/compare
register 0n0 (CR0n0) during timer counting, the change timing may conflict
with the timing of the match, so the operation is not guaranteed in such cases.
To change CR0n0 during timer counting, follow the procedure below using an
INTTM000 interrupt.
If CR010 is changed during timer counting without performing processing <1>
above, the value in CR010 may be rewritten twice or more, causing an
inversion of the output level of the TO00 pin at each rewrite.
The timing of the count start is after two valid edge detections.
When using an input pulse of the TI000 pin as a count clock (external trigger),
be sure to input the pulse width which satisfies the AC characteristics. For the
AC characteristics, refer to CHAPTER 21 and CHAPTER 22 ELECTRICAL
SPECIFICATIONS.
When an external waveform is input to 16-bit timer/event counter 00, it is
sampled by the noise limiter circuit and thus an error occurs on the timing to
become valid inside the device.
When changing the value of CR80, be sure to stop the timer operation. If the
value of CR80 is changed with the timer operation enabled, a match interrupt
request signal is generated immediately and the timer may be cleared.
Be sure to set TMC80 after stopping the timer operation.
Be sure to clear bits 0 and 6 to 0.
User's Manual U17446EJ3V1UD
Cautions
(6/19)
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