NEC 78K0S/KB1+ User Manual page 389

Function Details of
Function
8-bit timer Interval timer
80
Error when timer
starts
CR80: 8-bit
compare register
80
STOP mode
8-bit timer CMP01: 8-bit
H1 timer H compare
register 01
CMP11: 8-bit
timer H compare
register 11
TMHMD1: 8-bit
timer H mode
register 1
PWM output
Watchdog WDTM:
Watchdog timer
timer
mode register
APPENDIX D LIST OF CAUTIONS
When changing the value of CR80, be sure to stop the timer operation. If the
value of CR80 is changed with the timer operation enabled, a match interrupt
request signal may be generated immediately.
If the count clock of TMC80 is set and the operation of TM80 is enabled at the
same time by using an 8-bit memory manipulation instruction, the error of one
cycle after the timer is started may be 1 clock or more. Therefore, be sure to
follow the above sequence when using TM80 as an interval timer.
The time from starting the timer to generation of the match signal includes an
error of up to 1.5 clocks. This is because, if the timer is started while the count
clock is high, the rising edge may be immediately detected and the counter
may be incremented (refer to Figure 7-6).
8-bit compare register 80 (CR80) can be set to 00H.
Before executing the STOP instruction, be sure to stop the timer operation
(TCE80 = 0).
CMP01 cannot be rewritten during timer count operation.
In the PWM output mode, be sure to set CMP11 when starting the timer count
operation (TMHE1 = 1) after the timer count operation was stopped (TMHE1 =
0) (be sure to set again even if setting the same value to CMP11).
When TMHE1 = 1, setting the other bits of the TMHMD1 register is prohibited.
In the PWM output mode, be sure to set 8-bit timer H compare register 11
(CMP11) when starting the timer count operation (TMHE1 = 1) after the timer
count operation was stopped (TMHE1 = 0) (be sure to set again even if setting
the same value to the CMP11 register).
In PWM output mode, the setting value for the CMP11 register can be
changed during timer count operation. However, three operation clocks
(signal selected using the CKS12 to CKS10 bits of the TMHMD1 register) or
more are required to transfer the register value after rewriting the CMP11
register value.
Be sure to set the CMP11 register when starting the timer count operation
(TMHE1 = 1) after the timer count operation was stopped (TMHE1 = 0) (be
sure to set again even if setting the same value to the CMP11 register).
Make sure that the CMP11 register setting value (M) and CMP01 register
setting value (N) are within the following range.
00H ≤ CMP11 (M) < CMP01 (N) ≤ FFH
Set bits 7, 6, and 5 to 0, 1, and 1, respectively. Do not set the other values.
After reset is released, WDTM can be written only once by an 8-bit memory
manipulation instruction. If writing is attempted a second time, an internal
reset signal is generated. However, at the first write, if "1" and "x" are set for
WDCS4 and WDCS3 respectively and the watchdog timer is stopped, then the
internal reset signal does not occur even if the following are executed.
• Second write to WDTM
• 1-bit memory manipulation instruction to WDTE
• Writing of a value other than "ACH" to WDTE
User's Manual U17446EJ3V1UD
Cautions
(7/19)
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