NEC 78K0S/KB1+ User Manual page 384

Function Details of
Function
Main clock OSTS: Oscillation
stabilization time
select register
Crystal/
ceramic
oscillator
16-bit TM00: 16-bit
timer/event timer counter 00
counter 00
CR000: 16-bit
timer capture/
compare register
000
384
APPENDIX D LIST OF CAUTIONS
To set and then release the STOP mode, set the oscillation stabilization time
as follows.
Expected oscillation stabilization time of resonator ≤ Oscillation stabilization
time set by OSTS
The wait time after the STOP mode is released does not include the time from
the release of the STOP mode to the start of clock oscillation ("a" in the figure
below), regardless of whether STOP mode was released by reset signal
generation or interrupt generation.
The oscillation stabilization time that elapses on power application or after
release of reset is selected by the option byte. For details, refer to CHAPTER
18 OPTION BYTE.
−
When using the crystal/ceramic oscillator, wire as follows in the area enclosed
by the broken lines in Figure 5-6 to avoid an adverse effect from wiring
capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines. Do not route the wiring
near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential
as V . Do not ground the capacitor to a ground pattern through which a
SS
high current flows.
• Do not fetch signals from the oscillator.
Even if TM00 is read, the value is not captured by CR010.
When TM00 is read, count misses do not occur, since the input of the count
clock is temporarily stopped and then resumed after the read.
Set CR000 to other than 0000H in the clear & start mode entered on match
between TM00 and CR000. This means a 1-pulse count operation cannot be
performed when this register is used as an external event counter.
In the free-running mode and in the clear & start mode using the valid edge of
TI000 pin, if CR000 is set to 0000H, an interrupt request (INTTM000) is
generated when CR000 changes from 0000H to 0001H following overflow
(FFFFH).
If the new value of CR000 is less than the value of 16-bit timer counter 0
(TM00), TM00 continues counting, overflows, and then starts counting from 0
again. If the new value of CR000 is less than the old value, therefore, the
timer must be reset to be restarted after the value of CR000 is changed.
The value of CR000 after 16-bit timer/event counter 00 has stopped is not
guaranteed.
The capture operation may not be performed for CR000 set in compare mode
even if a capture trigger is input.
When using P31 as the input pin (TI010) of the valid edge, it cannot be used
as a timer output pin (TO00). When using P31 as the timer output pin (TO00),
it cannot be used as the input pin (TI010) of the valid edge.
User's Manual U17446EJ3V1UD
Cautions
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