NEC 78K0S/KB1+ User Manual page 82

V
DD
RESET
H
Internal reset
System clock
CPU clock
Note Operation stop time is 277
(a) The internal reset signal is generated by the power-on-clear function on power application, the option byte is
referenced after reset, and the system clock is selected.
(b) The option byte is referenced and the system clock is selected. Then the external clock operates as the
system clock.
Figure 5-13. Status Transition of Default Start by External Clock Input
Remark PCC: Processor clock control register
PPCC: Preprocessor clock control register
82
CHAPTER 5 CLOCK GENERATORS
Figure 5-12. Timing of Default Start by External Clock Input
(a)
Option byte is read.
System clock is selected.
(Operation stops
μ μ
s (MIN.), 544
Power
application
V
Reset by
power-on-clear
External clock input
selected by option byte
Start with PCC = 02H,
PPCC = 02H
Clock division ratio
variable during
CPU operation
Interrupt HALT
instruction
HALT
User's Manual U17446EJ3V1UD
(b)
External clock input
PCC = 02H, PPCC = 02H
Note
)
s (TYP.), and 1.075 ms (MAX.).
> 2.1 V ±0.1 V
DD
Reset signal
Interrupt
STOP
instruction
STOP