NEC 78K0S/KB1+ User Manual page 100

f
Noise eliminator
XP
Valid edge of TI000
Note OVF00 is 1 only when 16-bit timer capture/compare register 000 (CR000) is set to FFFFH.
Figure 6-16. External Event Counter Operation Timing (with Rising Edge Specified)
(1) INTTM000 generation timing immediately after operation starts
TI000 pin input
TM00 count value
CR000
INTTM000
(2) INTTM000 generation timing after INTTM000 has been generated twice
TI000 pin input
TM00 count value
N
CR000
INTTM000
Caution When reading the external event counter count value, TM00 should be read.
100
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-15. External Event Counter Configuration Diagram
Counting is started after a valid edge is detected twice.
Count starts
2 3
1
0000H 0001H 0002H 0003H
N
0000H 0001H 0002H 0003H 0004H
N
User's Manual U17446EJ3V1UD
Internal bus
16-bit timer capture/compare
register 000 (CR000)
Match
Clear
16-bit timer counter 00 (TM00)
N-2 N-1
N-1 N 0000H 0001H 0002H 0003H
INTTM000
Note
OVF00
N 0000H 0001H 0002H