Texas Instruments TPS65982 Manual

Texas Instruments TPS65982 Manual

Usb type-c and usb pd controller, power switch, and high-speed multiplexer
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TPS65982 USB Type-C

1 Features

This device is certified by the USB-IF for PD2.0
– PD2.0 is no longer certifiable on new designs
as of June 2020
– All new designs requiring certification should
use a PD3.0 compliant device
– Article on
PD2.0 vs PD3.0
Fully configurable USB PD controller
– Control for external DC/DC supplies through
GPIO
Ex:
TPS65982EVM
– Port data multiplexer
USB 2.0 HS data and low speed endpoint
Sideband-use data for alternate modes
GUI tool
to easily configure TPS65982 for
various applications
– Support for DisplayPort alternate mode and
thunderbolt alternate mode
– For a more extensive selection guide and
getting started information, please refer to
www.ti.com/usb-c
and
Integrated fully managed power paths:
– Integrated 5-V, 3-A, 50-mΩ sourcing switch
– Integrated 5-V to 20-V, 3-A, 95-mΩ bi-
directional load switch
– Gate control and current sense for external 5-V
to 20-V, 5-A bidirectional switch (back-to-back
NFETs)
– UL2367 cert#: E169910-20150728
– IEC62368-1 cert #: 111895
Integrated robust power path protection
– Integrated reverse current protection,
undervoltage protection, overvoltage protection,
and slew rate control the high-voltage bi-
directional power path
– Integrated undervoltage and overvoltage
protection and current limiting for inrush current
protection for the 5-V/3-A source power path
USB Type-C
®
Power Delivery (PD) controller
– 8 configurable GPIOs
– BC1.2 charging support
– USB PD 2.0 certified
– USB Type-C specification certified
– Cable attach and orientation detection
– Integrated VCONN switch
– Physical layer and policy engine
– 3.3-V LDO output for dead battery support
– Power supply from 3.3 V or VBUS source
– 1 I2C primary port
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
®
and USB PD Controller, Power Switch, and High-Speed
Multiplexer
E2E guide
SLVSD02E – MARCH 2015 – REVISED AUGUST 2021
– 1 I2C secondary port

2 Applications

Rugged PC and laptop
Docking station
Flat panel monitor

3 Description

The TPS65982 device is a stand-alone USB Type-C
and Power Delivery (PD) controller providing cable-
plug and orientation detection at the USB Type-
C connector. Upon cable detection, the TPS65982
device communicates on the CC wire using the USB
PD protocol. After successful USB PD negotiation
is complete, the TPS65982 enables the appropriate
power path and configures alternate mode settings for
internal and (optional) external multiplexers.
The mixed-signal front end on the CC pins advertises
default, 1.5 A or 3 A for USB Type-C power sources,
detects a plug event and determines the Type-C cable
orientation, and autonomously negotiates USB PD
contracts using a Bi-phase Marked Coding (BMC) and
the Physical Layer (PHY) protocol.
Device Information
PART NUMBER
PACKAGE
BGA MicroStar
Junior (96)
TPS65982
NFBGA (96)
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
5 to 20 V
External FET Sense and CTRL
5 to 20 V
3 A
5 V
3 A
3.3 V
Type-
Host
Detection
Host
Interface
USB PD Controller
High
USB2.0 and
Speed
Sideband-Use
Mux
Data
Alternate Mode Mux Ctrl
TPS65982
SuperSpeed Mux
Copyright © 2016, Texas Instruments Incorporated
Simplified Diagram
TPS65982
(1)
BODY SIZE (NOM)
6.00 mm × 6.00 mm
5 A
V
BUS
C Cable
CC/V
and
CC1/2
2
CONN
USB
Type-C
Connector
USB_TP/TN
2
USB_BP/BN
2
SBU1/2
2
SBU1/2
GND

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Summary of Contents for Texas Instruments TPS65982

  • Page 1: Features

    PD3.0 compliant device 3 Description – Article on PD2.0 vs PD3.0 The TPS65982 device is a stand-alone USB Type-C • Fully configurable USB PD controller and Power Delivery (PD) controller providing cable- – Control for external DC/DC supplies through...
  • Page 2: Table Of Contents

    Added the HRESET I/O voltage parameter to the Absolute Maximum Ratings table........11 • Changed the value for the HBM from ±2000 to ±1500 in the ESD Ratings table..........Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65982...
  • Page 3 Completed editorial changes to fix typographical errors and improve consistency of terminology.....1 Changes from Revision * (March 2015) to Revision A (June 2015) Page • Initial release of Production Data sheet......................Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65982...
  • Page 4 (device), or source-sink. The TPS65982 is also an upstream-facing port (UFP), downstream-facing port (DFP), or dual-role port for data. The port data multiplexer passes data to or from the top or bottom D+/D– signal pair at the port for USB 2.0 HS;...
  • Page 5: Pin Configuration And Functions

    Figure 6-1. ZQZ and ZBH Package 96-Pin BGA MicroStar Junior and NFBGA Top View Application High Power Low Power Ground GPIOs No Connect Specific Legend for Pinout Drawing Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65982...
  • Page 6 General purpose digital I/O 1. Float pin if it is configured as a push-pull Digital core I/O GPIO1 Digital I/O Hi-Z output in the application. Ground pin with a 1-MΩ resistor when unused in and control pins the application. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65982...
  • Page 7 Hi-Z (GPIO11) and control pins assert RESETZ when pulled low. Ground pin with a 1MΩ resistor when unused in the application. UART serial transmit data. Connect pin to another TPS65982 UART_TX to Digital Port multiplexer UART_TX UART_RX share firmware. Connect UART_RX to UART_TX when not connected to...
  • Page 8 Digital I/O (GPIO9) and control pins output (Low) low (driven low on start-up). Float pin when unused. UART serial receive data. Connect pin to another TPS65982 UART_TX to Port multiplexer UART_RX Digital input Digital input share firmware. Connect UART_RX to UART_TX when not connected to pins another TPS65982 and ground pin through a 100-kΩ...
  • Page 9 Analog I/O Hi-Z pins with between 1-kΩ and 5-MΩ resistance when unused. C_USB_TN Analog I/O Type-C port pins Hi-Z Port-side top USB D– connection to port multiplexer. Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65982...
  • Page 10 Port-side Sideband Use connection of port multiplexer. Output to Type-C CC or VCONN pin. Filter noise with capacitance CC_CC1 C_CC1 Analog I/O Type-C port pins Hi-Z to GND. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65982...
  • Page 11: Specifications

    JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions. Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links:...
  • Page 12: Recommended Operating Conditions

    Junction-to-top characterization parameter °C/W ψ Junction-to-board characterization parameter °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65982...
  • Page 13: Power Supply Requirements And Characteristics

    2.95 VOUT_3V3 output Bi-direction DC bus voltage. Output from the VBUS TPS65982 or input to the TPS65982 5V supply input to power VBUS. This supply does PP_5V0 4.75 not power the TPS65982...
  • Page 14: Power Supervisor Characteristics

    Application code can result in other power consumption measurements by adjusting enabled circuitry and clock rates. Application code also provisions the wake=up mechanisms (for example, I C activity and GPIO activity). Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65982...
  • Page 15: Cable Detection Characteristics

    Threshold Voltage of the pulldown FET in series with RD during VTH_DB I_CC = 80 μA dead battery R_RPD Resistance between RPD_Gn and the gate of the pulldown FET MΩ Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65982...
  • Page 16: Characteristics

    TX transmit peak voltage 1.14 1.26 VTXP7 TX transmit peak voltage 1.116 1.175 1.233 VTXP8 TX transmit peak voltage 1.092 1.15 1.208 VTXP9 TX transmit peak voltage 1.068 1.125 1.181 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65982...
  • Page 17 4.026 4.474 4.921 PP_HV current limit, setting 13 4.278 4.753 5.228 PP_HV current limit, setting 14 4.529 5.033 5.536 PP_HV current limit, setting 15 5.033 5.592 6.151 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65982...
  • Page 18 I = 100 mA Reverse current 1.95 4.05 blocking disabled I = 200 mA IPP5V_ACC PP_5V0 current sense accuracy I = 500 mA 2.64 3.36 I ≥ 1 A Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65982...
  • Page 19 Specified for a 10-mΩ RSENSE resistor and 10-mΩ RSENSE application code setting. Values will scale with a different RSENSE resistance and application code setting. Settings selected automatically by application code for the current limit needed in the application. Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links:...
  • Page 20 Time from disable bit at charge DB3_TOFF Switch off time from disable of DEBUG3/4 path pump steady state DB3_BW 3dB bandwidth of DEBUG3/4 path = 10 pF Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65982...
  • Page 21 All RON specified maximums are the maximum of either of the switches in a pair. All ROND specified maximums are the maximum difference between the two switches in a pair. ROND does not add to RON. Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback...
  • Page 22: Port Data Multiplexer Clamp Characteristics

    Signal falling The USB Endpoint PHY is functional across the entire VIN_3V3 operating range, but parameter values are only verified by design for VIN_3V3 ≥ 3.135 V Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65982...
  • Page 23: Characteristics

    GAIN_ERR Gain error (no divider) –1 VOS_ERR Buffer offset error –10 THERM_ACC Thermal sense accuracy –8 °C THERM_GAIN Thermal slope 3.095 mV/°C THERM_V0 Zero degree voltage 0.823 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65982...
  • Page 24: Input/Output (I/O) Characteristics

    μA = –8 mA, LDO_3V3=3.3 V SPI_VOH SPI output high voltage = –15 mA, LDO_3V3=3.3 V = 10 mA SPI_VOL SPI output low voltage = 20 mA Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65982...
  • Page 25 = 0 V to LDO_1V8D –1 μA HRESET_THIGH HRESET minimum high time to assert a reset condition HRESET_TLOW HRESET minimum low time to deassert a reset condition UART_RX/TX, LSX_P2R/R2P Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65982...
  • Page 26 C Valid data time SCL low to SDA output valid μs ACK signal from SCL low to SDA (out) TVDACK C Valid data time of ACK condition μs Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65982...
  • Page 27: Buspowerz Configuration Characteristics

    BUSPOWERZ Voltage for receiving VBUS Power through the VBPZ_EXT PP_EXT path BUSPOWERZ Voltage for receiving VBUS Power through the VBPZ_HV PP_HV path VBPZ_DIS BUSPOWERZ Voltage for disabling system power from VBUS Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65982...
  • Page 28: Thermal Shutdown Characteristics

    DP SINK SIDE (HPD RX) HPD_HDB_SEL = 0 μs T_HPD_HDB HPD high debounce time HPD_HDB_SEL = 1 T_HPD_LDB HPD low debounce time μs T_HPD_IRQ HPD IRQ limit time 1.35 1.65 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65982...
  • Page 29: Typical Characteristics

    Temperature (qC) D001 D002 Figure 7-1. PP_5V0 Switch On-Resistance vs. Figure 7-2. PP_HV Switch On-Resistance vs. Temperature Temperature Temperature (qC) D003 Figure 7-3. PP_CABLE Switch On-Resistance vs Temperature Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65982...
  • Page 30: Parameter Measurement Information

    Figure 8-2. ADC Enable and Conversion Timing T_SAMPA T_CONVERTA T_INTA T_SAMPLE T_CONVERTA ADC Clock ADC Sample ADC Interrupt New Valid Output New Valid Output ADC Output Figure 8-3. ADC Repeated Conversion Timing Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65982...
  • Page 31 Valid Data t hdpoci Figure 8-5. SPI Controller Timing whigh wlow SWD_CLK dout dout SWD_DATA (Output) Valid Data hdin suin SWD_DATA (Input) Valid Data Figure 8-6. SWD Timing Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65982...
  • Page 32: Detailed Description

    1.8 V or 3.3 V rail. The TPS65982 is an I C slave to...
  • Page 33: Functional Block Diagram

    9.3 Feature Description 9.3.1 USB-PD Physical Layer Figure 9-1 shows the USB PD physical layer block surrounded by a simplified version of the analog plug and orientation detection block. Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65982...
  • Page 34 4b5b Data to PD_TX Encoder Encoder Figure 9-2. USB-PD Baseband Transmitter Block Diagram Data 4b5b from PD_RX Decoder Detect Decoder Figure 9-3. USB-PD Baseband Receiver Block Diagram Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65982...
  • Page 35 USB-PD Specifications for more details. 9.3.1.4 USB-PD BMC Transmitter The TPS65982 transmits and receives USB-PD data over one of the C_CCn pins. The C_CCn pin is also used to determine the cable orientation (see the Cable Plug and Orientation Detection section) and maintain cable/device attach detection.
  • Page 36 ZDRIVER. It is specified such that noise at the receiver is bounded. ZDRVER is defined by Equation R DRIVER ZDRIVER 1 s R + ´ ´ DRIVER DRIVER Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65982...
  • Page 37 9.3.2.1 Configured as a DFP When configured as a DFP, the TPS65982 detects when a cable or a UFP is attached using the C_CC1 and C_CC2 pins. When in a disconnected state, the TPS65982 monitors the voltages on these pins to determine what, if anything, is connected.
  • Page 38 Mode attached When the TPS65982 is configured as a DFP, a current IH_CC is driven out each C_CCn pin and each pin is monitored for different states. When a UFP is attached to the pin, a pulldown resistance of Rd to GND will exist.
  • Page 39 Figure 9-10. C_CCn and RPD_Gn pins When C_CC1 is shorted to RPD_G1 and C_CC2 is shorted to RPD_G2 in an application of the TPS65982, booting from dead-battery or no-battery conditions will be supported. In this case, the gate driver for the pulldown FET is Hi-Z at its output.
  • Page 40 Figure 9-11. Port Power Paths 9.3.3.1 5V Power Delivery The TPS65982 provides port power to VBUS from PP_5V0 when a low voltage output is needed. The switch path provides 5 V at up to 3 A to from PP_5V0 to VBUS.
  • Page 41 2 Ω. I VBUS VBUS Time (5 Ps/div) D004 Figure 9-13. PP_5V0 Current Limit with a Hard Short Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65982...
  • Page 42 9.3.3.6 Internal HV Power Switch as a Source The TPS65982 provides power from PP_HV to VBUS at the USB Type-C port as an output when operating as a source. When the switch is on as a source, the path behaves resistively until the current reaches the amount Submit Document Feedback Copyright ©...
  • Page 43 9.3.3.7 Internal HV Power Switch as a Sink The TPS65982 can also receive power from VBUS to PP_HV when operating as a sink. When the switch is on as a sink the path behaves as an ideal diode and blocks reverse current from PP_HV to VBUS.
  • Page 44 The external path may be used in conjunction with the internal path. For example, the internal path may be used to source current from PP_HV to VBUS when the TPS65982 is acting as a power source and the external path may be used to sink current from VBUS to PP_EXT to charge a battery when the TPS65982 is acting as a sink.
  • Page 45 9.3.3.13 External HV Power Switch as a Sink without RSENSE Figure 9-21 shows the configuration when the TPS65982 is acting as a sink for the external switch path without an RSENSE resistor. In this mode, current is sunk from VBUS to an internal system power node, referred to as PP_EXT.
  • Page 46 Battery or No-Battery Support, the TPS65982 will appear as a USB Type-C sink (device) causing a connected USB Type-C source (host) to provide 5 V on VBUS. The TPS65982 will power itself from the 5-V VBUS rail (see Power Management) and execute boot code (see Boot Code).
  • Page 47 When the voltage on BUSPOWERZ is in the VBPZ_DIS range (when BUSPOWERZ is tied to LDO_3V3 as in Figure 9-22), this indicates that the TPS65982 will not route the 5 V present on VBUS to the entire system. In this case, the TPS65982 will load SPI-connected flash memory and execute this application code. This configuration will disable both the PP_HV and PP_EXT high voltage switches and only use VBUS to power the TPS65982.
  • Page 48 Figure 9-26. Negative Voltage Transition on VBUS 9.3.3.19 HV Transition to PP_RV0 Pull-Down on VBUS The TPS65982 has an integrated active pulldown on VBUS when transitioning from PP_HV to PP_5V0, shown Figure 9-27. When the PP_HV switch is disabled and VBUS > PP_5V0 + VHVDISPD, amplifier turns on a current source and pulls down on VBUS.
  • Page 49 See the Section 9.3.2 section for more detailed information on plug and orientation detection. Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65982...
  • Page 50 C_CC1 USB-PD Digital Core Power LDO_3V3 C_CC2 VCONN Active Cable Circuitry Cable Plug C_CC2 Gate Control Figure 9-29. Port C_CC1 and C_CC2 Normal Orientation Power from PP_CABLE Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65982...
  • Page 51 The switch does not have reverse current blocking when the switch is enabled and current is flowing to either C_CC1 or C_CC2. Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links:...
  • Page 52 Figure 9-31. PP_CABLE to C_CCn Current Limit with a Hard Short I CC2 C_CC2 PP_CABLE Time (500 Ps/div) D010 Figure 9-32. PP_CABLE to C_CCn Current Limit with a Hard Short (Extended Time Base) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65982...
  • Page 53 There are two USB output ports that may or may not be passing USB data. When an Alternate Mode is connected, these same ports may also pass that data (e.g. DisplayPort, Thunderbolt). Note, the TPS65982 pin to receptacle mapping is shown in Table 9-2.
  • Page 54 TPS65982 www.ti.com SLVSD02E – MARCH 2015 – REVISED AUGUST 2021 Table 9-2. TPS65982 to USB Type-C Receptacle Mapping (continued) DEVICE PIN Type-C RECEPTACLE PIN C_SBU2 SBU2 (B8) SWD_DATA SWD_CLK GPIO0 GPIO1 GPIO UART0 1st Stage 2nd Stage Digital Cross-Bar Mux...
  • Page 55 Figure 9-35. The connections are configurable via firmware. The default state at power-up is to connect a buffered version of UART_RX to UART_TX providing a bypass through the TPS65982 for daisy chaining during power on reset. 9.3.4.4 SBU Crossbar Multiplexer The SBU Crossbar Multiplexer provides pins (C_SBU1 and C_SBU2) for future USB functionality as well as Alternate Modes.
  • Page 56 SLVSD02E – MARCH 2015 – REVISED AUGUST 2021 9.3.4.5 Signal Monitoring and Pullup/Pulldown The TPS65982 has comparators that may be enabled to interrupt the core when a switching event occurs on any of the port inputs. The input parameters for the detection are listed in the...
  • Page 57 The USB low-speed Endpoint is a USB 2.0 low-speed (1.5 Mbps) interface used to support HID class based accesses. The TPS65982 supports control of endpoint EP0. This endpoint enumerates to a USB 2.0 bus to provide USB-Billboard information to a host system as defined in the USB Type-C standard. EP0 is used for advertising the Billboard Class.
  • Page 58 ADC integrated in the TPS65982. To provide complete flexibility, 12 independent switches are connected to allow firmware to force voltage, sink current, and read voltage on any of the C_USB_TP, C_USB_TN, C_USB_BP, and C_USB_BN.
  • Page 59 The other way a supply switch-over will occur is when both supplies are present and VIN_3V3 is removed and falls below 2.85 V. In this case, a hard reset of the TPS65982 occurs prompting a re-boot.
  • Page 60 VOUT_3V3 is disabled, a resistance of RPDOUT_3V3 pulls down on the pin. 9.3.6 Digital Core Figure 9-41 shows a simplified block diagram of the digital core. This diagram shows the interface between the digital and analog portions of the TPS65982. HRESET MRESET RESETZ...
  • Page 61 W25Q80DV 8 Mbit Serial Flash Memory. A memory of at least 2 Mbit is required when the TPS65982 is using the memory in an unshared manner. A memory of at least 8 Mbit is required when the TPS65982 is using the memory in an shared manner.
  • Page 62 Debounce State HPD_IRQ Interrupt Timer passes Low_Debounce Timer Passes S4: HPD IRQ IRQ_Limit HPD GPIO goes Detect State high before Timer reaches IRQ_Limit Figure 9-42. HPD RX Flow Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65982...
  • Page 63 The output from the ADC is available to be read and used by application firmware. Each supply voltage into the TPS65982 is available to be converted including the port power path inputs and outputs. All GPIO, the C_CCn pins, the charger detection voltages are also available for conversion. To read the port power path current sourced to VBUS, the high-voltage and low-voltage power paths are sensed and converted to voltages to be read by the ADC.
  • Page 64 Voltage IPP_5V0 Current CC1_BY5 Voltage IPP_CABLE Current CC2_BY5 Voltage GPIO5 Voltage CC1_BY2 Voltage CC2_BY2 Voltage PP_CABLE Voltage VIN_3V3 Voltage VOUT_3V3 Voltage BC_ID Voltage LDO_1V8A Voltage LDO_1V8D Voltage Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65982...
  • Page 65 Round Robin Automatic Readout, the channel averaging must be set to 1 sample. When the TPS65982 is running a Round Robin Readout, it will take approximately 696 μs (11 channels × 63.33 μs conversion) to fully convert all channels. Since the conversion is continuous, when a channel is converted, it will overwrite the previous result.
  • Page 66 VDDIO is fail-safe and a diode will not be present from GPIOn to VDDIO in this configuration. The pullup and pulldown output drivers are independently controlled from the input and are enabled or disabled via application code in the digital core. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65982...
  • Page 67 CMOS output driver as the GPIO buffer. The output has independent pulldown control allowing open-drain connections. OD_DO Figure 9-47. IOBUF_OD Output Buffer Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65982...
  • Page 68 C clock and data I/Os are found in Section 7.20. 50 ns I2C_DI Deglitch I2C_IRQnZ I2C_DO Figure 9-51. IOBUF_I2C I/O 9.3.18.7 IOBUF_GPIOHSPI Figure 9-52 shows the I/O buffers for the SPI interface. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65982...
  • Page 69 9.3.19 Thermal Shutdown The TPS65982 has both a central thermal shutdown to the chip and a local thermal shutdown for the power path block. The central thermal shutdown monitors the temperature of the center of the die and disables all functions except for supervisory circuitry and halts digital core when die temperature goes above a rising temperature of TSD_MAIN.
  • Page 70: Device Functional Modes

    C address is based on the customer programmable OTP, DEBUG_CTLX pins, and resistor configuration on the I2C_ADDR pin. Once initial device configuration is complete the boot code determines if the TPS65982 is booting under dead battery condition (VIN_3V3 invalid, VBUS valid). If the boot code determines the TPS65982 is booting under dead battery condition, the BUSPOWERZ pin is sampled to determine the appropriate path for routing VBUS power to the system.
  • Page 71 VIN_3V3, the dead battery flow is followed to allow for the rest of the system to receive power. The state of the BUSPOWERZ pin is read to determine power path configuration for dead battery operation. After the power path is configured, the TPS65982 will continue through the boot process. Figure 9-56 shows the full dead battery process.
  • Page 72 Figure 9-56. Dead-Battery Condition Flow Diagram 9.4.5 Application Code The TPS65982 application code is stored in an external flash memory. The flash memory used for storing the TPS65982 application code may be shared with other devices in the system. The flash memory organization...
  • Page 73 The TPS65982 first attempts to load application code from the low region of the attached flash memory. If any part of the read process yields invalid data, the TPS65982 will abort the low region read and attempt to read from the high region. If both regions contain invalid data the device carries out the Invalid Memory flow.
  • Page 74 Figure 9-58. Flash Read Flow 9.4.7 Invalid Flash Memory If the flash memory read fails because of invalid data, the TPS65982 carries out the memory invalid flow and presents the SWD interface on the USB Type-C SBU pins. Figure 9-59 shows the invalid memory process.
  • Page 75 Present SWD Monitor VBUS Figure 9-59. Memory Invalid Flow 9.4.8 UART Download the secondary TPS65982 downloads the needed application code from the primary TPS65982 via UART. Figure 9-60 shows the UART download process. Currently the TPS65982 firmware only supports 2 device (1 primary + 1 secondary) systems.
  • Page 76: Programming

    SPI_CLK pin is held (or idling) low. The minimum erasable sector size of the flash must be 4 kB. The W25Q80 flash memory IC is recommended. Refer to TPS65982 I C Host Interface Specification for instructions for interacting with the attached flash memory over SPI using the host interface of the TPS65982. 9.5.2 I C Slave Interface The TPS65982 has three I C interface ports.
  • Page 77 9.5.2.1 I C Interface Description The TPS65982 support Standard and Fast mode I C interface. The bidirectional I C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be connected to a supply through a pullup resistor. Data transfer may be initiated only when the bus is not busy.
  • Page 78 9.5.2.3 I C Address Setting The boot code sets the hardware configurable unique I C address of the TPS65982 before the port is enabled to respond to I C transactions. The unique I C address is determined by a combination of the digital level on the...
  • Page 79 C Pin Address Setting To enable the setting of multiple I C addresses using a single TPS65982 pin, a resistance is placed externally on the I2C_ADDR pin. The internal ADC then decodes the address from this resistance value. Figure 9-67 shows the decoding.
  • Page 80 C Unique Address. For the Primary TPS65982 (UART Master), the I2C_ADDR pin is grounded and this TPS65982 is connected to the SPI Flash. In a two Type-C port system sharing one SPI Flash, I2C_ADDR is left as an open-circuit (UART Slave 1) and this TPS65982 is referred to as the Secondary.
  • Page 81: Application And Implementation

    Type C PD charger that is capable of supporting 5 V at 3 A, 12 V at 3 A, and 20 V at 5 A. The 5 V and 12 V outputs are supported by the TPS65982 internal FETs and the 20-V output uses the external FET path controlled by the TPS65982 NFET drive.
  • Page 82 IC, but a recommended minimum of 1 MB is needed when the flash memory of the TPS65982 is shared with another IC. This size will allow for pointers and two copies of the firmware image to reside on the flash along with the needed headers.
  • Page 83 10.2.1.2.4 VBUS Capacitor and Ferrite Bead A 1-µF ceramic capacitor is placed close to the TPS65982 VBUS pins. A 6 A ferrite bead is used in this design along with four high frequency noise 10-nF capacitors placed close to the Type-C connector to minimize noise.
  • Page 84 HD3SS460, to route the appropriate super-speed signals to the Type-C connector. The HD3SS460 is controlled through GPIOs configured by the TPS65982 application code and the HD3SS460 is designed to meet the timing requirements defined by the DisplayPort over Type-C specification. A system controller is also necessary to handle some of the dynamic aspects of Power Delivery such as reducing power capabilities when system battery power is low.
  • Page 85 (SS MUX) ML0 – ML3 DP Source SSTX/RX USB3 SSTX/RX USB3 Source Copyright © 2016, Texas Instruments Incorporated Figure 10-3. Dual-Port Notebook Application 10.2.2.1 Design Requirements For a dual-port notebook application, Table 10-3 lists the input voltage requirements and expected current capabilities.
  • Page 86 System Controller to change the sink profile when a power contract is established. When the DC barrel jack is connected the TPS65982 is renegotiate the a PD contract to no longer charge of Type C and have the DC Barrel Jack take precedence when connected.
  • Page 87 Type-C or Type-C to barrel jack. When the DC barrel jack is detected the TPS65982 at each Type-C port will not request 20 V for charging and the system will be able to support a Copyright ©...
  • Page 88 TPS65982. When the TPS65982 that is not connected to the flash is connected in dead battery it will pass the 5 V from VBUS in to the battery charger where the battery would be able to generate the needed System 3.3 V rail to both of the TPS65982s.
  • Page 89 C channels and the system to allow I C access to the TPS65982 from an external tool. A header is used to allow for connections without soldering; however, SMT test pads can be used to provide a place to solder blue-wires for testing.
  • Page 90: Power Supply Recommendations

    VBUS when VIN_3V3 is not available. This LDO steps down any recommended voltage on the VBUS pin. When VBUS is 20 V, as is allowable by USB PD, the internal circuitry of the TPS65982 will operate without triggering thermal shutdown; however, a significant external load on the LDO_3V3 pin may increase temperature enough to trigger thermal shutdown.
  • Page 91 11.3.2 Schottky for Current Surge Protection To prevent the possibility of large ground currents into the TPS65982 during sudden disconnects because of inductive effects in a cable, it is recommended that a Schottky be placed from VBUS to GND as shown in Figure 11-1.
  • Page 92: Layout

    Proper routing and placement will maintain signal integrity for high-speed signals and improve the thermal dissipation from the TPS65982 power path. The combination of power and high-speed data signals are easily routed if the following guidelines are followed. It is a best practice to consult with a printed circuit board (PCB) manufacturer to verify manufacturing capabilities.
  • Page 93 0.25 mm by 0.17 mm. All of the other non-oval shaped pads will have a 0.25 mm diameter. This footprint is recommended for MDI (Medium Density) PCB designs that are generally less expensive to build. The void under the TPS65982 allows for vias to route the inner signals and connect to the GND and power planes. Figure 12-5 shows the recommended minimum via size (8mil hole and 16 mil diameter).
  • Page 94 12.1.3 Top TPS65982 Placement and Bottom Component Placement and Layout When the TPS65982 is placed on top and its components on bottom the solution size will be at its smallest. For systems that do not use the optional external FET path the solution size will average less than 64 mm (8 mm ×...
  • Page 95 12.1.9 Void Via Placement The void under the TPS65982 is used to via out I/O and for thermal relief vias. A minimum of 6 vias must be used for thermal dissipation to the GND planes. The thermal relief vias must be placed on the right side of the device by the power path.
  • Page 96: Layout Example

    TPS65982 www.ti.com SLVSD02E – MARCH 2015 – REVISED AUGUST 2021 12.2 Layout Example Figure 12-6. Example Layout (Top View in 2-D) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65982...
  • Page 97 TPS65982 www.ti.com SLVSD02E – MARCH 2015 – REVISED AUGUST 2021 Figure 12-7. Example Layout (Bottom View in 2-D) Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65982...
  • Page 98 TPS65982 www.ti.com SLVSD02E – MARCH 2015 – REVISED AUGUST 2021 Figure 12-8. Example Layout (Top View in 3-D) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65982...
  • Page 99 TPS65982 www.ti.com SLVSD02E – MARCH 2015 – REVISED AUGUST 2021 Figure 12-9. Example Layout (Bottom View in 3-D) Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65982...
  • Page 100 TPS65982 www.ti.com SLVSD02E – MARCH 2015 – REVISED AUGUST 2021 Figure 12-10. Top Polygonal Pours Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65982...
  • Page 101 TPS65982 www.ti.com SLVSD02E – MARCH 2015 – REVISED AUGUST 2021 Figure 12-11. Bottom Polygonal Pours Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65982...
  • Page 102 TPS65982 www.ti.com SLVSD02E – MARCH 2015 – REVISED AUGUST 2021 Figure 12-12. CC1 and CC2 Capacitor Routing Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65982...
  • Page 103 TPS65982 www.ti.com SLVSD02E – MARCH 2015 – REVISED AUGUST 2021 Figure 12-13. Top Layer Component Routing Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65982...
  • Page 104 TPS65982 www.ti.com SLVSD02E – MARCH 2015 – REVISED AUGUST 2021 Figure 12-14. Bottom Layer Component Routing Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65982...
  • Page 105 TPS65982 www.ti.com SLVSD02E – MARCH 2015 – REVISED AUGUST 2021 Figure 12-15. Void Via Placement Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65982...
  • Page 106 TPS65982 www.ti.com SLVSD02E – MARCH 2015 – REVISED AUGUST 2021 Figure 12-16. Top Layer GND Pour Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65982...
  • Page 107 TPS65982 www.ti.com SLVSD02E – MARCH 2015 – REVISED AUGUST 2021 Figure 12-17. Final Routing and GND Pour (Top Layer) Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65982...
  • Page 108 TPS65982 www.ti.com SLVSD02E – MARCH 2015 – REVISED AUGUST 2021 Figure 12-18. Final Routing (Inner Signal Layer) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65982...
  • Page 109 TPS65982 www.ti.com SLVSD02E – MARCH 2015 – REVISED AUGUST 2021 Figure 12-19. Final Routing (Bottom Layer) Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65982...
  • Page 110: Device And Documentation Support

    All trademarks are the property of their respective owners. 13.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
  • Page 111 Call TI Level-3-260C-168 HR -10 to 85 TPS65982 The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
  • Page 112 PACKAGE MATERIALS INFORMATION www.ti.com 8-Jun-2022 TAPE AND REEL INFORMATION REEL DIMENSIONS TAPE DIMENSIONS B0 W Reel Diameter Cavity Dimension designed to accommodate the component width Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE...
  • Page 113 PACKAGE MATERIALS INFORMATION www.ti.com 8-Jun-2022 TAPE AND REEL BOX DIMENSIONS Width (mm) *All dimensions are nominal Device Package Type Package Drawing Pins Length (mm) Width (mm) Height (mm) TPS65982ABZBHR NFBGA 2500 336.6 336.6 31.8 Pack Materials-Page 2...
  • Page 114 PACKAGE OUTLINE ZBH0096A NFBGA - 1 mm max height SCALE 2.000 PLASTIC BALL GRID ARRAY BALL A1 CORNER INDEX AREA (0.65) 1 MAX SEATING PLANE BALL TYP 0.08 C 0.25 0.19 5 TYP SYMM (0.5) TYP (0.5) TYP SYMM 0.35 0.25 0.15 0.05...
  • Page 115 NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS NOT TO SCALE 4221754/B 09/2018 NOTES: (continued) 4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99). www.ti.com...
  • Page 116 EXAMPLE STENCIL DESIGN ZBH0096A NFBGA - 1 mm max height PLASTIC BALL GRID ARRAY 96X ( 0.25) (0.5) TYP (R0.05) TYP (0.5) TYP METAL SYMM SYMM SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:20X 4221754/B 09/2018 NOTES: (continued) 5.
  • Page 117 TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated...

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