Overview of HAL drivers
2.11
HAL system peripheral handling
This chapter gives an overview of how the system peripherals are handled by the HAL
drivers. The full API list is provided within each peripheral driver description section.
2.11.1
Clock
Two main functions can be used to configure the system clock:
HAL_RCC_OscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct). This function
configures/enables multiple clock sources (HSE, HSI, LSE, LSI, PLL).
HAL_RCC_ClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t
FLatency). This function
Some peripheral clocks are not derived from the system clock (RTC, SDIO, I2S, Audio,
PLL...). In this case, the clock configuration is performed by an extended API defined in
stm32f2xx_hal_rcc_ex.c: HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef
*PeriphClkInit).
Additional RCC HAL driver functions are available:
HAL_RCC_DeInit() Clock de-init function that return clock configuration to reset state
Get clock functions that allow retreiving various clock configurations (system clock,
HCLK, PCLK1, PCLK2, ...)
MCO and CSS configuration functions
A set of macros are defined in stm32f2xx_hal_rcc.h and stm32f2xx_hal_rcc_ex.h. They
allow executing elementary operations on RCC block registers, such as peripherals clock
gating/reset control:
__PPP_CLK_ENABLE/__PPP_CLK_DISABLE to enable/disable the peripheral clock
__PPP_FORCE_RESET/__PPP_RELEASE_RESET to force/release peripheral reset
__PPP_CLK_SLEEP_ENABLE/__PPP_CLK_SLEEP_DISABLE to enable/disable the
peripheral clock during low power (Sleep) mode.
2.11.2
GPIOs
GPIO HAL APIs are the following:
HAL_GPIO_Init() / HAL_GPIO_DeInit()
HAL_GPIO_ReadPin() / HAL_GPIO_WritePin()
HAL_GPIO_TogglePin ().
In addition to standard GPIO modes (input, output, analog), the pin mode can be
configured as EXTI with interrupt or event generation.
When selecting EXTI mode with interrupt generation, the user must call
HAL_GPIO_EXTI_IRQHandler() from stm32f2xx_it.c and implement
HAL_GPIO_EXTI_Callback().
The table below describes the GPIO_InitTypeDef structure field.
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selects the system clock source
configures AHB, APB1 and APB2 clock dividers
configures the number od Flash memory wait states
updates the SysTick configuration when HCLK clock changes.
DocID028236 Rev 2
UM1940
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