ST STM32F2 User Manual page 771

UM1940
LL_ADC_MULTI_DUAL_INJ_ALTERN
LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM
LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT
LL_ADC_MULTI_TRIPLE_INJ_SIMULT
LL_ADC_MULTI_TRIPLE_REG_SIMULT
LL_ADC_MULTI_TRIPLE_REG_INTERL
LL_ADC_MULTI_TRIPLE_INJ_ALTERN
Multimode - Delay between two sampling phases
LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES
LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES
LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES
LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES
LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES
LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES
LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES
LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES
ADC dual mode enabled: group injected
alternate trigger. Works only with external
triggers (not internal SW start)
ADC dual mode enabled: Combined
group regular simultaneous + group
injected simultaneous
ADC dual mode enabled: Combined
group regular simultaneous + group
injected alternate trigger
ADC dual mode enabled: Combined
group regular interleaved + group
injected simultaneous
ADC triple mode enabled: Combined
group regular simultaneous + group
injected simultaneous
ADC triple mode enabled: Combined
group regular simultaneous + group
injected alternate trigger
ADC triple mode enabled: group injected
simultaneous
ADC triple mode enabled: group regular
simultaneous
ADC triple mode enabled: Combined
group regular interleaved
ADC triple mode enabled: group injected
alternate trigger. Works only with external
triggers (not internal SW start)
DocID028236 Rev 2
LL ADC Generic Driver
ADC multimode delay between two
sampling phases: 5 ADC clock cycles
ADC multimode delay between two
sampling phases: 6 ADC clock cycles
ADC multimode delay between two
sampling phases: 7 ADC clock cycles
ADC multimode delay between two
sampling phases: 8 ADC clock cycles
ADC multimode delay between two
sampling phases: 9 ADC clock cycles
ADC multimode delay between two
sampling phases: 10 ADC clock cycles
ADC multimode delay between two
sampling phases: 11 ADC clock cycles
ADC multimode delay between two
sampling phases: 12 ADC clock cycles
ADC multimode delay between two
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