UM1940
36
HAL RCC Generic Driver
36.1
RCC Firmware driver registers structures
36.1.1
RCC_PLLInitTypeDef
Data Fields
uint32_t PLLState
uint32_t PLLSource
uint32_t PLLM
uint32_t PLLN
uint32_t PLLP
uint32_t PLLQ
Field Documentation
uint32_t RCC_PLLInitTypeDef::PLLState
The new state of the PLL. This parameter can be a value of
uint32_t RCC_PLLInitTypeDef::PLLSource
RCC_PLLSource: PLL entry clock source. This parameter must be a value of
RCC_PLL_Clock_Source
uint32_t RCC_PLLInitTypeDef::PLLM
PLLM: Division factor for PLL VCO input clock. This parameter must be a number
between Min_Data = 0 and Max_Data = 63
uint32_t RCC_PLLInitTypeDef::PLLN
PLLN: Multiplication factor for PLL VCO output clock. This parameter must be a
number between Min_Data = 192 and Max_Data = 432
uint32_t RCC_PLLInitTypeDef::PLLP
PLLP: Division factor for main system clock (SYSCLK). This parameter must be a
value of
uint32_t RCC_PLLInitTypeDef::PLLQ
PLLQ: Division factor for OTG FS, SDIO and RNG clocks. This parameter must be a
number between Min_Data = 2 and Max_Data = 15
36.1.2
RCC_OscInitTypeDef
Data Fields
uint32_t OscillatorType
uint32_t HSEState
uint32_t LSEState
uint32_t HSIState
uint32_t HSICalibrationValue
uint32_t LSIState
RCC_PLLInitTypeDef PLL
Field Documentation
uint32_t RCC_OscInitTypeDef::OscillatorType
The oscillators to be configured. This parameter can be a value of
RCC_Oscillator_Type
uint32_t RCC_OscInitTypeDef::HSEState
The new state of the HSE. This parameter can be a value of
RCC_PLLP_Clock_Divider
DocID028236 Rev 2
HAL RCC Generic Driver
RCC_PLL_Config
RCC_HSE_Config
417/1371
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