Cortex Firmware Driver Defines - ST STM32F2 User Manual

LL CORTEX Generic Driver
Function description
Parameters
Return values
Reference Manual to
LL API cross
reference:
52.2

CORTEX Firmware driver defines

52.2.1 CORTEX
MPU Bufferable Access
LL_MPU_ACCESS_BUFFERABLE
LL_MPU_ACCESS_NOT_BUFFERABLE
MPU Cacheable Access
LL_MPU_ACCESS_CACHEABLE
LL_MPU_ACCESS_NOT_CACHEABLE
SYSTICK Clock Source
LL_SYSTICK_CLKSOURCE_HCLK_DIV8
LL_SYSTICK_CLKSOURCE_HCLK
MPU Control
LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
LL_MPU_CTRL_HARDFAULT_NMI
LL_MPU_CTRL_PRIVILEGED_DEFAULT
LL_MPU_CTRL_HFNMI_PRIVDEF
Handler Fault type
LL_HANDLER_FAULT_USG
LL_HANDLER_FAULT_BUS
LL_HANDLER_FAULT_MEM
MPU Instruction Access
826/1371
Region)
Disable a region.
Region: This parameter can be one of the following values:
LL_MPU_REGION_NUMBER0
LL_MPU_REGION_NUMBER1
LL_MPU_REGION_NUMBER2
LL_MPU_REGION_NUMBER3
LL_MPU_REGION_NUMBER4
LL_MPU_REGION_NUMBER5
LL_MPU_REGION_NUMBER6
LL_MPU_REGION_NUMBER7
None:
MPU_RNR REGION LL_MPU_DisableRegion
MPU_RASR ENABLE LL_MPU_DisableRegion
Bufferable memory attribute
Not Bufferable memory attribute
Cacheable memory attribute
Not Cacheable memory attribute
AHB clock divided by 8 selected as SysTick
clock source.
AHB clock selected as SysTick clock source.
Disable NMI and privileged SW access
Enables the operation of MPU during hard
fault, NMI, and FAULTMASK handlers
Enable privileged software access to default
memory map
Enable NMI and privileged SW access
Usage fault
Bus fault
Memory management fault
DocID028236 Rev 2
UM1940