Hal Iwdg Generic Driver; Iwdg_Inittypedef; Iwdg_Handletypedef; Iwdg Generic Features - ST STM32F2 User Manual

UM1940
27

HAL IWDG Generic Driver

27.1

IWDG Firmware driver registers structures

27.1.1

IWDG_InitTypeDef

Data Fields
uint32_t Prescaler
uint32_t Reload
Field Documentation
uint32_t IWDG_InitTypeDef::Prescaler
Select the prescaler of the IWDG. This parameter can be a value of
uint32_t IWDG_InitTypeDef::Reload
Specifies the IWDG down-counter reload value. This parameter must be a number
between Min_Data = 0 and Max_Data = 0x0FFF
27.1.2

IWDG_HandleTypeDef

Data Fields
IWDG_TypeDef * Instance
IWDG_InitTypeDef Init
Field Documentation
IWDG_TypeDef* IWDG_HandleTypeDef::Instance
Register base address
IWDG_InitTypeDef IWDG_HandleTypeDef::Init
IWDG required parameters
27.2

IWDG Firmware driver API description

27.2.1

IWDG Generic features

The IWDG can be started by either software or hardware (configurable through option
byte).
The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even if the main
clock fails.
Once the IWDG is started, the LSI is forced ON and both can not be disabled. The
counter starts counting down from the reset value (0xFFF). When it reaches the end of
count value (0x000) a reset signal is generated (IWDG reset).
Whenever the key value 0x0000 AAAA is written in the IWDG_KR register, the
IWDG_RLR value is reloaded in the counter and the watchdog reset is prevented.
The IWDG is implemented in the VDD voltage domain that is still functional in STOP
and STANDBY mode (IWDG reset can wake-up from STANDBY). IWDGRST flag in
RCC_CSR register can be used to inform when an IWDG reset occurs.
Debug mode : When the microcontroller enters debug mode (core halted), the IWDG
counter either continues to work normally or stops, depending on DBG_IWDG_STOP
configuration bit in DBG module, accessible through
__HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG()
macros
DocID028236 Rev 2
HAL IWDG Generic Driver
IWDG_Prescaler
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