ST STM32F2 User Manual page 772

Description of stm32f2 hal and low layer drivers
Hide thumbs Also See for STM32F2:
Table of Contents

Advertisement

LL ADC Generic Driver
LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES
LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES
LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES
LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES
LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES
LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES
LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES
ADC registers compliant with specific purpose
LL_ADC_DMA_REG_REGULAR_DATA
LL_ADC_DMA_REG_REGULAR_DATA_MULTI
ADC group regular - Continuous mode
LL_ADC_REG_CONV_SINGLE
LL_ADC_REG_CONV_CONTINUOUS
ADC group regular - DMA transfer of ADC conversion data
LL_ADC_REG_DMA_TRANSFER_NONE
LL_ADC_REG_DMA_TRANSFER_LIMITED
LL_ADC_REG_DMA_TRANSFER_UNLIMITED
ADC group regular - Flag EOC selection (unitary or sequence conversions)
LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV
LL_ADC_REG_FLAG_EOC_UNITARY_CONV
772/1371
ADC conversions are performed in single mode:
one conversion per trigger
ADC conversions are performed in continuous
mode: after the first trigger, following conversions
launched successively automatically
ADC conversions are not transferred by
DMA
ADC conversion data are transferred by
DMA, in limited mode (one shot mode):
DMA transfer requests are stopped
when number of DMA data transfers
(number of ADC conversions) is
reached. This ADC mode is intended to
be used with DMA mode non-circular.
ADC conversion data are transferred by
DMA, in unlimited mode: DMA transfer
requests are unlimited, whatever number
of DMA data transferred (number of
ADC conversions). This ADC mode is
intended to be used with DMA mode
circular.
DocID028236 Rev 2
sampling phases: 13 ADC clock cycles
ADC multimode delay between two
sampling phases: 14 ADC clock cycles
ADC multimode delay between two
sampling phases: 15 ADC clock cycles
ADC multimode delay between two
sampling phases: 16 ADC clock cycles
ADC multimode delay between two
sampling phases: 17 ADC clock cycles
ADC multimode delay between two
sampling phases: 18 ADC clock cycles
ADC multimode delay between two
sampling phases: 19 ADC clock cycles
ADC multimode delay between two
sampling phases: 20 ADC clock cycles
ADC flag EOC (end of unitary
conversion) selected
ADC flag EOS (end of sequence
UM1940

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the STM32F2 and is the answer not in the manual?

Questions and answers

Table of Contents

Save PDF