Eth Dma Rx Descriptor Buffers; Eth Dma Transmit Process State; Eth Dma Tx Descriptor - ST STM32F2 User Manual

HAL ETH Generic Driver

ETH DMA Rx descriptor buffers

ETH_DMARXDESC_BUFFER1
ETH_DMARXDESC_BUFFER2

ETH DMA transmit process state

ETH_DMA_TRANSMITPROCESS_STOPPED
ETH_DMA_TRANSMITPROCESS_FETCHING
ETH_DMA_TRANSMITPROCESS_WAITING
ETH_DMA_TRANSMITPROCESS_READING
ETH_DMA_TRANSMITPROCESS_SUSPENDED
ETH_DMA_TRANSMITPROCESS_CLOSING

ETH DMA TX Descriptor

ETH_DMATXDESC_OWN
ETH_DMATXDESC_IC
ETH_DMATXDESC_LS
ETH_DMATXDESC_FS
ETH_DMATXDESC_DC
ETH_DMATXDESC_DP
ETH_DMATXDESC_TTSE
ETH_DMATXDESC_CIC
ETH_DMATXDESC_CIC_BYPASS
ETH_DMATXDESC_CIC_IPV4HEADER
ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT
ETH_DMATXDESC_CIC_TCPUDPICMP_FULL
ETH_DMATXDESC_TER
ETH_DMATXDESC_TCH
ETH_DMATXDESC_TTSS
ETH_DMATXDESC_IHE
ETH_DMATXDESC_ES
ETH_DMATXDESC_JT
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DMA Rx Desc Buffer1
DMA Rx Desc Buffer2
DocID028236 Rev 2
Stopped - Reset or Stop Tx Command
issued
Running - fetching the Tx descriptor
Running - waiting for status
Running - reading the data from host
memory
Suspended - Tx Descriptor
unavailable
Running - closing Rx descriptor
OWN bit: descriptor is owned by
DMA engine
Interrupt on Completion
Last Segment
First Segment
Disable CRC
Disable Padding
Transmit Time Stamp Enable
Checksum Insertion Control: 4
cases
Do Nothing: Checksum Engine is
bypassed
IPV4 header Checksum Insertion
TCP/UDP/ICMP Checksum
Insertion calculated over segment
only
TCP/UDP/ICMP Checksum
Insertion fully calculated
Transmit End of Ring
Second Address Chained
Tx Time Stamp Status
IP Header Error
Error summary: OR of the
following bits: UE || ED || EC ||
LCO || NC || LCA || FF || JT
Jabber Timeout
UM1940