HAL I2S Generic Driver
HAL_I2S_Transmit_IT
Function name
Function description
Parameters
Return values
Notes
HAL_I2S_Receive_IT
Function name
Function description
Parameters
Return values
Notes
320/1371
In I2S Master Receiver mode, just after enabling the
peripheral the clock will be generate in continuous way and as
the I2S is not disabled at the end of the I2S transaction.
HAL_StatusTypeDef HAL_I2S_Transmit_IT
(I2S_HandleTypeDef * hi2s, uint16_t * pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
hi2s: pointer to a I2S_HandleTypeDef structure that contains
the configuration information for I2S module
pData: a 16-bit pointer to data buffer.
Size: number of data sample to be sent:
HAL: status
When a 16-bit data frame or a 16-bit data frame extended is
selected during the I2S configuration phase, the Size
parameter means the number of 16-bit data length in the
transaction and when a 24-bit data frame or a 32-bit data
frame is selected the Size parameter means the number of
16-bit data length.
The I2S is kept enabled at the end of transaction to avoid the
clock de-synchronization between Master and Slave(example:
audio streaming).
HAL_StatusTypeDef HAL_I2S_Receive_IT
(I2S_HandleTypeDef * hi2s, uint16_t * pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
hi2s: pointer to a I2S_HandleTypeDef structure that contains
the configuration information for I2S module
pData: a 16-bit pointer to the Receive data buffer.
Size: number of data sample to be sent:
HAL: status
When a 16-bit data frame or a 16-bit data frame extended is
selected during the I2S configuration phase, the Size
parameter means the number of 16-bit data length in the
transaction and when a 24-bit data frame or a 32-bit data
frame is selected the Size parameter means the number of
16-bit data length.
The I2S is kept enabled at the end of transaction to avoid the
clock de-synchronization between Master and Slave(example:
audio streaming).
It is recommended to use DMA for the I2S receiver to avoid
de-synchronisation between Master and Slave otherwise the
I2S interrupt should be optimized.
DocID028236 Rev 2
UM1940
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