Rcc Limitations; Initialization And De-Initialization Functions - ST STM32F2 User Manual

UM1940
Configure the System clock frequency and Flash settings
Configure the AHB and APB busses prescalers
Enable the clock for the peripheral(s) to be used
Configure the clock source(s) for peripherals which clocks are not derived from the
System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
36.2.2

RCC Limitations

A delay between an RCC peripheral clock enable and the effective peripheral enabling
should be taken into account in order to manage the peripheral read/write from/to registers.
This delay depends on the peripheral mapping.
If peripheral is mapped on AHB: the delay is 2 AHB clock cycle after the clock enable
bit is set on the hardware register
If peripheral is mapped on APB: the delay is 2 APB clock cycle after the clock enable
bit is set on the hardware register
Implemented Workaround:
For AHB & APB peripherals, a dummy read to the peripheral register has been
inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
36.2.3

Initialization and de-initialization functions

This section provides functions allowing to configure the internal/external oscillators (HSE,
HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1
and APB2).
Internal/external clock and PLL configuration
1. HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through the
PLL as System clock source.
2. LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
clock source.
3. HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or through the
PLL as System clock source. Can be used also as RTC clock source.
4. LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
5. PLL (clocked by HSI or HSE), featuring two different output clocks:
6. CSS (Clock security system), once enable using the macro
__HAL_RCC_CSS_ENABLE() and if a HSE clock failure occurs(HSE used directly or
through PLL as System clock source), the System clocks automatically switched to
HSI and an interrupt is generated if enabled. The interrupt is linked to the Cortex-M3
NMI (Non-Maskable Interrupt) exception vector.
7. MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL clock
(through a configurable prescaler) on PA8 pin.
8. MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
clock (through a configurable prescaler) on PC9 pin.
System, AHB and APB busses clocks configuration
1. Several clock sources can be used to drive the System clock (SYSCLK): HSI, HSE
and PLL. The AHB clock (HCLK) is derived from System clock through configurable
prescaler and used to clock the CPU, memory and peripherals mapped on AHB bus
(DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived from AHB
clock through configurable prescalers and used to clock the peripherals mapped on
these busses. You can use "HAL_RCC_GetSysClockFreq()" function to retrieve the
The first output is used to generate the high speed system clock (up to 120 MHz)
The second output is used to generate the clock for the USB OTG FS (48 MHz),
the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
DocID028236 Rev 2
HAL RCC Generic Driver
419/1371