Rcc_Clkinittypedef; Rcc Firmware Driver Api Description; Rcc Specific Features - ST STM32F2 User Manual

HAL RCC Generic Driver
uint32_t RCC_OscInitTypeDef::LSEState
The new state of the LSE. This parameter can be a value of
uint32_t RCC_OscInitTypeDef::HSIState
The new state of the HSI. This parameter can be a value of
uint32_t RCC_OscInitTypeDef::HSICalibrationValue
The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F
uint32_t RCC_OscInitTypeDef::LSIState
The new state of the LSI. This parameter can be a value of
RCC_PLLInitTypeDef RCC_OscInitTypeDef::PLL
PLL structure parameters
36.1.3

RCC_ClkInitTypeDef

Data Fields
uint32_t ClockType
uint32_t SYSCLKSource
uint32_t AHBCLKDivider
uint32_t APB1CLKDivider
uint32_t APB2CLKDivider
Field Documentation
uint32_t RCC_ClkInitTypeDef::ClockType
The clock to be configured. This parameter can be a value of
RCC_System_Clock_Type
uint32_t RCC_ClkInitTypeDef::SYSCLKSource
The clock source (SYSCLKS) used as system clock. This parameter can be a value of
RCC_System_Clock_Source
uint32_t RCC_ClkInitTypeDef::AHBCLKDivider
The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
This parameter can be a value of
uint32_t RCC_ClkInitTypeDef::APB1CLKDivider
The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
This parameter can be a value of
uint32_t RCC_ClkInitTypeDef::APB2CLKDivider
The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
This parameter can be a value of
36.2

RCC Firmware driver API description

36.2.1

RCC specific features

After reset the device is running from Internal High Speed oscillator (HSI 16MHz) with
Flash 0 wait state, Flash prefetch buffer, D-Cache and I-Cache are disabled, and all
peripherals are off except internal SRAM, Flash and JTAG.
There is no prescaler on High speed (AHB) and Low speed (APB) busses; all
peripherals mapped on these busses are running at HSI speed.
The clock for all peripherals is switched off, except the SRAM and FLASH.
All GPIOs are in input floating state, except the JTAG pins which are assigned to be
used for debug purpose.
Once the device started from reset, the user application has to:
Configure the clock source to be used to drive the System clock (if the application
needs higher frequency/performance)
418/1371
RCC_AHB_Clock_Source
RCC_APB1_APB2_Clock_Source
RCC_APB1_APB2_Clock_Source
DocID028236 Rev 2
UM1940
RCC_LSE_Config
RCC_HSI_Config
RCC_LSI_Config