NEC 78K0S/KA1+ User Manual page 300

8-bit single-chip microcontrollers
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Figure 18-25. Example of Internal Verify Operation in Self Programming Mode
Note This setting is not required when the watchdog timer is not used.
Remark
<1> to <11> in Figure 18-25 correspond to <1> to <11> in 18.8.9 (previous page).
300
CHAPTER 18 FLASH MEMORY
Internal verify
<1> Set internal verify
command (FLCMD = 01H)
<2> Set no. of block for
internal verify, to FLAPH
<3> Set start address to FLAPL
<4> Set the same value as
that of FLAPH to FLAPHC
<5>
Set end address to
FLAPLC
<6> Clear PFS
<7> Clear & restart WDT counter
Note
(WDTE = ACH)
<8> Execute HALT instruction
<9> Check execution result
(VCERR and WEPRERR flags)
Normal
<11> Normal termination
User's Manual U16898EJ3V0UD
Abnormal
<10> Abnormal termination

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