NEC 78K0S/KA1+ User Manual page 184

Figure 11-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (2/2)
RXE6
0
1
PS61
0
0
1
1
CL6
0
1
SL6
0
1
ISRM6
0
1
Note If "reception as 0 parity" is selected, the parity is not judged. Therefore, bit 2 (PE6) of asynchronous serial
interface reception error status register 6 (ASIS6) is not set and the error interrupt does not occur.
Cautions 1. At startup, set POWER6 to 1 and then set TXE6 to 1. To stop the operation, clear TXE6 to 0,
and then clear POWER6 to 0.
2. At startup, set POWER6 to 1 and then set RXE6 to 1. To stop the operation, clear RXE6 to 0,
and then clear POWER6 to 0.
3. Set POWER6 to 1 and then set RXE6 to 1 while a high level is input to the RxD6 pin. If
POWER6 is set to 1 and RXE6 is set to 1 while a low level is input, reception is started.
4. Clear the TXE6 and RXE6 bits to 0 before rewriting the PS61, PS60, and CL6 bits.
5. Fix the PS61 and PS60 bits to 0 when mounting the device on LIN.
6. Make sure that TXE6 = 0 when rewriting the SL6 bit. Reception is always performed with "the
number of stop bits = 1", and therefore, is not affected by the set value of the SL6 bit.
7. Make sure that RXE6 = 0 when rewriting the ISRM6 bit.
184
CHAPTER 11 SERIAL INTERFACE UART6
Disable reception (synchronously reset the reception circuit).
Enable reception
PS60 Transmission operation
0 Parity bit not output.
1 Output 0 parity.
0 Output odd parity.
1 Output even parity.
Specification of character length of transmit/receive data
Character length of data = 7 bits
Character length of data = 8 bits
Specification of number of stop bits of transmit data
Number of stop bits = 1
Number of stop bits = 2
Enabling/disabling occurrence of reception completion interrupt in case of error
"INTSRE6" occurs in case of error (at this time, INTSR6 does not occur).
"INTSR6" occurs in case of error (at this time, INTSRE6 does not occur).
User's Manual U16898EJ3V0UD
Enabling/disabling reception
Reception without parity
Reception as 0 parity
Judge as odd parity.
Judge as even parity.
Reception operation
Note