NEC 78K0S/KA1+ User Manual page 405

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p. 117 Modification of <1> in (11) One-shot pulse output by software of 6.5 Cautions Related to 16-Bit
Timer/Event Counter 00
p. 118 Modification of <1> in (12) One-shot pulse output with external trigger of 6.5 Cautions Related to 16-Bit
Timer/Event Counter 00
p. 119 Modification of <3> in (15) Capture operation of 6.5 Cautions Related to 16-Bit Timer/Event Counter 00
p. 121 Modification of <1> in (19) External event counter of 6.5 Cautions Related to 16-Bit Timer/Event Counter 00
p. 124 Modification of Caution in (1) 8-bit compare register 80 (CR80) of 7.2 Configuration of 8-Bit Timer 80
p. 131 Modification of description in (2) 8-bit timer H compare register 11 (CMP11) of 8.2 Configuration of 8-Bit
Timer H1
p. 139 Modification of Caution 1 in 8.4.2 Operation as PWM output mode
p. 143 Modification of (e) Operation by changing CMP11 (CMP11 = 02H → 03H, CMP01 = A5H) in Figure 8-9.
Operation Timing in PWM Output Mode
p. 148 Addition of description to Caution 2 in Figure 9-2. Format of Watchdog Timer Mode Register (WDTM)
p. 156 Modification of Figure 10-1. Timing of A/D Converter Sampling and A/D Conversion
p. 157 Modification of Table 10-1. Sampling Time and A/D Conversion Time and Note 1
pp. 161, 162 Modification of Figure 10-3. Format of A/D Converter Mode Register (ADM) and Note 2
p. 173 Modification of (4) Noise countermeasures in 10.6 Cautions for A/D Converter
p. 173 Modification of (6) Input impedance of ANI0 to ANI3 pins in 10.6 Cautions for A/D Converter
p. 177 Modification of Figure 11-1. LIN Transmission Operation
p. 178 Modification of Figure 11-2. LIN Reception Operation and description
p. 191 Addition of description to (7) Input switch control register (ISC) in 11.3 Registers Controlling Serial
Interface UART6
p. 210 Modification of value in Table 11-4. Set Data of Baud Rate Generator
p. 214 Modification of 12.1 Interrupt Function Types
p. 224 Modification of 12.4.2 Multiple interrupt servicing
p. 225 Addition of Caution to Example 1 in Figure 12-10. Example of Multiple Interrupts (1/2)
p. 226 Addition of Example 3 to Figure 12-10. Example of Multiple Interrupts (1/2)
p. 232 Modification of reset signal in Figure 13-3. HALT Mode Release by Reset Signal Generation
p. 233 Modification of description in External interrupt of Table 13-4. Operating Statuses in STOP Mode
p. 235 Modification of description in and addition of Note to (a) Release by unmasked interrupt request in (2) of
13.2.2 STOP mode
p. 236 Modification of reset signal in Figure 13-6. STOP Mode Release by Reset Signal Generation
p. 238 Modification of Figure 14-1. Block Diagram of Reset Function
pp. 239, 241 Addition of delay time of internal reset signal generation to Figure 14-2. Timing of Reset by RESET Input
and Figure 14-4. Reset Timing by RESET Input in STOP Mode
p. 247 Modification of Figure 15-3. Example of Software Processing After Release of Reset (1/2)
p. 249 Modification of Figure 16-1. Block Diagram of Low-Voltage Detector
p. 250 Modification of Note 1 in Figure 16-2. Format of Low-Voltage Detect Register (LVIM)
p. 251 Modification of Note in Figure 16-3. Format of Low-Voltage Detection Level Select Register (LVIS)
p. 255 Modification of INTLVI and Note 2 in Figure 16-5. Timing of Low-Voltage Detector Interrupt Signal
Generation
p. 256 Modification of (2) in <Action> of 16.5 Cautions for Low-Voltage Detector
APPENDIX E REVISION HISTORY
Description
User's Manual U16898EJ3V0UD
(2/3)
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