NEC 78K0S/KA1+ User Manual page 70

The fastest instruction of the 78K0S/KA1+ is executed in two CPU clocks. Therefore, the relationship between the
CPU clock (f ) and the minimum instruction execution time is as shown in Table 5-2.
CPU
Table 5-2. Relationship Between CPU Clock and Minimum Instruction Execution Time
Note
CPU Clock (f )
CPU
f
X
f /2
X
2
f /2
X
3
f /2
X
4
f /2
X
Note The CPU clock (high-speed internal oscillation clock, crystal/ceramic oscillation clock, or external clock
input) is selected by the option byte.
(2) Low-speed internal oscillation mode register (LSRCM)
This register is used to select the operation mode of the low-speed internal oscillator (240 kHz (TYP.)).
This register is valid when it is specified by the option byte that the low-speed internal oscillator can be stopped
by software. If it is specified by the option byte that the low-speed internal oscillator cannot be stopped by
software, setting of this register is invalid, and the low-speed internal oscillator continues oscillating. In addition,
the source clock of WDT is fixed to the low-speed internal oscillator.
WATCHDOG TIMER.
LSRCM can be set by using a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets LSRCM to 00H.
Figure 5-4. Format of Low-Speed internal oscillation Mode Register (LSRCM)
Address: FF58H After reset: 00H R/W
Symbol 7
LSRCM 0
LSRSTOP
0
1
70
CHAPTER 5 CLOCK GENERATORS
Minimum Instruction Execution Time: 2/f
High-speed internal oscillation clock
(at 8.0 MHz (TYP.))
µ
0.25 s
µ
0.5 s
µ
1.0 s
µ
2.0 s
µ
4.0 s
6 5
0 0
Oscillation/stop of low-speed internal oscillator
Low-speed internal oscillates
Low-speed internal oscillator stops
User's Manual U16898EJ3V0UD
Crystal/ceramic oscillation clock
or external clock input (at 10.0 MHz)
µ
0.2 s
µ
0.4 s
µ
0.8 s
µ
1.6 s
µ
3.2 s
For details, refer to CHAPTER 9
4 3 2
0 0 0
CPU
1 <0>
0 LSRSTOP