NEC 78K0S/KA1+ User Manual page 71

(3) Oscillation stabilization time select register (OSTS)
This register is used to select oscillation stabilization time of the clock supplied from the oscillator when the STOP
mode is released. The wait time set by OSTS is valid only when the crystal/ceramic oscillation clock is selected
as the system clock and after the STOP mode is released. If the high-speed internal oscillator or external clock
input is selected as the system clock source, no wait time elapses.
The system clock oscillator and the oscillation stabilization time that elapses after power application or release of
reset are selected by the option byte. For details, refer to CHAPTER 17 OPTION BYTE.
OSTS is set by using an 8-bit memory manipulation instruction.
Figure 5-5. Format of Oscillation Stabilization Time Select Register (OSTS)
Address: FFF4H After reset: Undefined R/W
Symbol 7
OSTS 0
OSTS1
0
0
1
1
Cautions 1. To set and then release the STOP mode, set the oscillation stabilization time as follows.
Expected oscillation stabilization time of resonator ≤ Oscillation stabilization time set by
OSTS
2. The wait time after the STOP mode is released does not include the time from the release of
the STOP mode to the start of clock oscillation ("a" in the figure below), regardless of
whether STOP mode was released by reset signal generation or interrupt generation.
3. The oscillation stabilization time that elapses on power application or after release of reset is
selected by the option byte. For details, refer to CHAPTER 17 OPTION BYTE.
Remarks 1. ( ): f = 10 MHz
X
2. Determine the oscillation stabilization time of the resonator by checking the characteristics of the
resonator to be used.
CHAPTER 5 CLOCK GENERATORS
6 5
0 0
OSTS0
10
µ
0 2 /f (102.4 s)
X
12
µ
1 2 /f (409.6 s)
X
15
0 2 /f (3.27 ms)
X
17
1 2 /f (13.1 ms)
X
STOP mode is released
Voltage
waveform
of X1 pin
User's Manual U16898EJ3V0UD
4 3 2
0 0 0
Selection of oscillation stabilization time
a
1 0
OSTS1 OSTS0
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