NEC 78K0S/KA1+ User Manual page 79

Figure 5-12. Timing of Default Start by External Clock Input
V
DD
RESET
H
Internal reset
System clock
CPU clock
Note Operation stop time is 277
(a) The internal reset signal is generated by the power-on clear function on power application, the option byte is
referenced after reset, and the system clock is selected.
(b) The option byte is referenced and the system clock is selected. Then the external clock operates as the
system clock.
Figure 5-13. Status Transition of Default Start by External Clock Input
Interrupt
Remark PCC: Processor clock control register
PPCC: Preprocessor clock control register
CHAPTER 5 CLOCK GENERATORS
(a)
Option byte is read.
System clock is selected.
Note
(Operation stops )
µ µ
s (MIN.), 544 s (TYP.), and 1.075 ms (MAX.).
Power
application
> 2.1 V ±0.1 V
V
DD
Reset by
power-on clear
External clock input
selected by option byte
Start with PCC = 02H,
PPCC = 02H
Clock division ratio
variable during
CPU operation
HALT
instruction
STOP
instruction
HALT
User's Manual U16898EJ3V0UD
(b)
External clock input
PCC = 02H, PPCC = 02H
Reset signal
Interrupt
STOP
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