NEC 78K0S/KA1+ User Manual page 240

Figure 14-3. Timing of Reset by Overflow of Watchdog Timer
<1> With high-speed internal oscillation clock or external clock input
High-speed internal oscillation clock or
external clock input
CPU clock
Watchdog overflow
Internal reset signal
Port pin
(except P130)
Port pin
(P130)
Notes 1. The operation stop time is 277
2. Set high level output using software.
Caution The watchdog timer is also reset in the case of an internal reset of the watchdog timer.
Remark When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is
effected, the output signal of P130 can be dummy-output as the reset signal to the CPU.
Crystal/ceramic
oscillation clock
CPU clock
Watchdog overflow
Internal reset signal
Port pin
(except P130)
Port pin
(P130)
Notes 1. The operation stop time is 276
2. Set high level output using software.
Caution The watchdog timer is also reset in the case of an internal reset of the watchdog timer.
Remark 1. f : System clock oscillation frequency
X
2. When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is
effected, the output signal of P130 can be dummy-output as the reset signal to the CPU.
240
CHAPTER 14 RESET FUNCTION
Normal operation
in progress
µ
s (MIN.), 544
<2> With crystal/ceramic oscillation clock
Normal operation
in progress (oscillation stops)
µ
s (MIN.), 544
User's Manual U16898EJ3V0UD
Reset period
(oscillation stops)
Operation stops because option
byte is referenced
µ
s (TYP.), and 1.075 ms (MAX.).
Reset period Oscillation stabilization
10 17
time (2 /f to 2 /f )
X X
Operation stops because option
byte is referenced
Hi-Z
µ
s (TYP.), and 1.074 ms (MAX.).
Normal operation (reset processing, CPU clock)
Note 1
.
Hi-Z
Note 2
Normal operation
(reset processing, CPU clock)
Note 1
.
Note 2