NEC 78K0S/KA1+ User Manual page 118

(12) One-shot pulse output with external trigger
<1> Do not input the external trigger again while the one-shot pulse is output. To output the one-shot pulse
again, wait until the current one-shot pulse output is completed.
<2> Do not set the 16-bit timer capture/compare registers 000 and 010 (CR000 and CR010) to 0000H.
(13) Operation of OVF00 flag
<1> The OVF00 flag is also set to 1 in the following case.
Either of the clear & start mode entered on a match between TM00 and CR000, clear & start at the valid
edge of the TI000 pin, or free-running mode is selected.
CR000 is set to FFFFH.
When TM00 is counted up from FFFFH to 0000H.
<2> Even if the OVF00 flag is cleared before the next count clock is counted (before TM00 becomes 0001H)
after the occurrence of a TM00 overflow, the OVF00 flag is re-set newly and clear is disabled.
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
↓
↓
Figure 6-37. Operation Timing of OVF00 Flag
Count clock
CR000 FFFFH
TM00
FFFEH
OVF00
INTTM000
User's Manual U16898EJ3V0UD
FFFFH 0000H 0001H