NEC 78K0S/KA1+ User Manual page 267
8-bit single-chip microcontrollers
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Also See for 78K0S/KA1+:
- Preliminary user's manual (304 pages) ,
- Application note (49 pages) ,
- Application note (44 pages)
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Table 18-2. Wiring Between 78K0S/KA1+ and FlashPro4
FlashPro4 Connection Pin
Pin Name
I/O
Note
CLK
Output
Note
FLMD0
Output
Note
SI/RxD
Input
Note
SO/TxD
Output
/RESET
Output
V
–
DD
GND
–
Note In the 78K0S/KA1+, the CLK and FLMD0 signals are connected to the X1 pin and the SI/RxD and SO/TxD
signals to the X2 signal; therefore, these signals need to be directly connected.
PG-FPL2 Connection Pin
Pin Name
I/O
CLK
Output
DGDATA
I/O
/RESET
Output
V
–
DD
GND
–
CHAPTER 18 FLASH MEMORY
Pin Function
Clock to 78K0S/KA1+
On-board mode signal
Receive signal
Receive signal/on-board mode signal
Reset signal
V
voltage generation/voltage monitor
DD
Ground
Figure 18-4. Wiring diagram with FlashPro4
FlashPro4
signal name
CLK
FLMD0
SI/RxD
SO/TxD
/RESET
V
DD
GND
Table 18-3. Wiring Between 78K0S/KA1+ and PG-FPL2
Pin Function
Clock to 78K0S/KA1+
Transmit/receive signal, on-board mode signal
Reset signal
V
voltage generation
DD
Ground
Figure 18-5. Wiring diagram with PG-FPL2
PG-FPL2
signal name
DGCLK
DGDATA
/RESET
V
DD
GND
User's Manual U16898EJ3V0UD
78K0S/KA1+ Connection Pin
Pin Name
X1/P121
X2/P122
RESET/P34
V
DD
V
SS
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
78K0S/KA1+
78K0S/KA1+ Connection Pin
Pin Name
X1/P121
X2/P122
RESET/P34
V
DD
V
SS
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
78K0S/KA1+
Pin No.
2
3
6
5
1
Pin No.
2
3
6
5
1
267
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