NEC 78K0S/KA1+ User Manual page 278

Figure 18-13. Format of Flash Protect Command Register (PFCMD)
Address: FFA0H
Symbol 7
PFCMD REG7
(3) Flash status register (PFS)
If data is not written to the flash programming mode control register (FLPMC), which is protected, in the correct
sequence (writing the flash protect command register (PFCMD)), FLPMC is not written and a protection error
occurs. If this happens, bit 0 of PFS (FPRERR) is set to 1.
When FPRERR is 1, it can be cleared to 0 by writing 0 to it.
Errors that may occur during self programming are reflected in bit 1 (VCERR) and bit 2 (WEPRERR) of PFS.
VCERR or WEPRERR can be cleared by writing 0 to them.
All the flags of the PFS register must be pre-cleared to 0 to check if the operation is performed correctly.
PFS can be set with a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears PFS to 00H.
Address: FFA1H
Symbol 7
PFS 0
1. Operating conditions of FPRERR flag
<Setting conditions>
• If PFCMD is written when the store instruction operation recently performed on a peripheral register is not to
write a specific value (A5H) to FLPMC
• If the first store instruction operation after <1> is on a peripheral register other than FLPMC
• If the first store instruction operation after <2> is on a peripheral register other than FLPMC
• If a value other than the inverted value of the value to be set to FLPMC is written by the first store instruction
after <2>
• If the first store instruction operation after <3> is on a peripheral register other than FLPMC
• If a value other than the value to be set to FLPMC (value written in <2>) is written by the first store instruction
after <3>
Remark The numbers in angle brackets above correspond to the those in (2) Flash protect command
register (PFCMD).
<Reset conditions>
• If 0 is written to the FPRERR flag
• If the reset signal is generated
2. Operating conditions of VCERR flag
<Setting conditions>
• Erasure verification error
• Internal writing verification error
278
CHAPTER 18 FLASH MEMORY
After reset: Undefined W
6 5
REG6 REG5 REG4
Figure 18-14. Format of Flash Status Register (PFS)
After reset: 00H R/W
6 5
0 0
User's Manual U16898EJ3V0UD
4 3 2
REG3 REG2
4 3 2
0 0
WEPRERR
1 0
REG1 REG0
1 0
VCERR FPRERR