Clock Generator; Clock Generator Configuration; Block Diagram Of The Clock Generator - NEC PD750004 User Manual

µPD750008 USER'S MANUAL

5.2 CLOCK GENERATOR

The clock generator supplies various clock signals to the CPU and peripheral hardware to control the CPU
operation mode.

5.2.1 Clock Generator Configuration

Figure 5-11 shows the configuration of the clock generator.
XT1
XT2
X1
X2
WM.3
SCC
SCC3
SCC0
PCC
PCC0
PCC1
4
PCC2
Note
HALT
PCC3
Note
STOP
PCC2, PCC3
clear signal
Note Instruction execution
Remarks 1. f : Main system clock frequency
X
2. f : Subsystem clock frequency
XT
3. F = CPU clock
4. PCC: Processor clock control register
5. SCC: System clock control register
6. One clock cycle (t
84
Figure 5-11. Block Diagram of the Clock Generator
f
Subsystem
XT
Clock timer
clock generator
f
X
Main system
clock generator
Oscillator
disable
signal
STOP flip-flop
Q S
R
) of the CPU clock (F) is equal to one machine cycle of an instruction.
CY
1/1 to 1/4096
Frequency divider
1/2 1/4 1/16
Selec-
tor
Selec-
tor
HALT flip-flop
S
R Q
• Basic interval timer (BT)
• Timer/event counter
• Timer counter
• Serial interface
• Clock timer
• INT0 noise eliminator
• Clock output circuit
Frequency
divider
1/4
CPU
•
INT0 noise eliminator
•
Clock output circuit
•
Wait release signal from BT
RESET signal
Standby release signal from
interrupt control circuit