Clock Generator Circuit - NEC mPD75512 Datasheet

6.2

CLOCK GENERATOR CIRCUIT

The operation of the clock generator circuit is determined by the processor clock control regiser (PPC) and
system clock control register (SCC).
This circuit can generate two types of clocks: main system clock and subsystem clock.
In addition, it can also change the instruction execution time.
• 0.95 µ s, 1.91 µ s, 15.3 µ s (main system clock: 4.19 MHz)
• 122 µ s (subsystem clock: 32.768 kHz)
V
DD
V
DD
WM.3
SCC3
SCC0
PCC0
PCC1
4
PCC2
HALT*
PCC3
STOP*
PCC2, PCC3
clear signal
*: instruction execution.
Remarks 1: f = Main system clock frequency
X
2: f = Subsystem clock frequency
XT
3: Φ = CPU clock
4: PCC: Processor clock control register
5: SCC: System clock control register
6: One clock cycle (t
characteristics in 11. ELECTRICAL SPECIFICATIONS.
20
XT1
Subsystem
f
XT
clock Watch timer
XT2
oscillator
Timer/pulse
generator
X1
Main system
f
X
clock
X2
oscillator
SCC
Oscillator
disable
signal
PCC
STOP F/F
Q S
R
) of Φ is one machine cycle of an instruction. For t
CY
Fig. 6-1 Clock Generator Block Diagram
· Basic interval timer (BT)
· Timer/event counter
· Serial interface
· Watch timer
· Clock output circuit
· A/D converter
· INT0 noise rejecter circuit
1/8 to 1/4096
Frequency divider
1/2 1/16
HALT F/F
S
R Q
Wait release
signal from BT
RESET signal
Standby release
signal from interrupt
control circuit
µ PD75512
Frequency
divider
Φ
1/4
· CPU
· INT0 noise
rejecter circuit
· Clock output
circuit
, refer to AC
CY