Intel ® Mch System Bus Interface; Figure 48. Thermtrip# Power Down Sequence; Figure 49. Voltage Divider Network For Reference Voltage Generation - Intel Pentium 4 Design Manual

System Bus Routing

Figure 48. THERMTRIP# Power Down Sequence

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5.5 Intel
A voltage divider network should supply host interface reference voltages locally as shown in
Figure 49, Figure 50 and as specified by Table 20.

Figure 49. Voltage Divider Network for Reference Voltage Generation

NOTES:
1. The MCH has only one dedicated voltage divider.
2. Decouple the voltage divider with a 1 µF capacitor.
3. Keep the voltage divider within 1.5 inches of the MCH Vref ball
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THERMTRIP# Power Down Sequence
THERMTRIP#
VID_GOOD
VCC_CPU
PWRGOOD
T1 < 0.5 seconds
Note: VID_GOOD is not a processor signal. This signal
is routed to the output enable pin of the voltage regluator
control silicon.
MCH System Bus Interface
Vcc
R2
R1
® ®
Intel Pentium 4 Processor / Intel
T1
THERMTRIP_PWR-Down_Sequence
L1 = 1.5" max
TLine
1 uF
®
850 Chipset Family Platform Design Guide
Socket Pin
220 pF
V-Div_Ref_Gen
R