Ddr Memory Ecc Functionality Disable; System Memory Compensation; Smvref Generation; Ddr Power Delivery - Intel 852GME Design Manual

R
Example 1
SO-DIMM0
SCK0,1,2
SMAA[1,2,4,5]
SCKE0,1; SCS#0,1
On platforms where ECC memory is supported, it is important that all relevant SDQ, SDQS, and SCK
signals to the SO-DIMMs be disabled when the system is populated with only non-ECC or a
combination of ECC and non-ECC memory.
Please contact your Intel field representative for information on memory initialization and register
programming.
6.5.2.

DDR Memory ECC Functionality Disable

It is imperative that systems that do not support ECC memory ensure the SCK clock pairs that are
normally sent to ECC SO-DIMMs be disabled. If the SCK clock pairs associated with the check bit
signals were left floating in a non-ECC memory only system and ECC memory was used in one or more
of the SO-DIMM slots, this could cause the ECC device on the SO-DIMM to be enabled. If SDQ[71:64]
is disabled/tri-stated or not routed, then these floating inputs can cause the ECC device to draw current
and potentially compromise the ECC device.
In JEDEC PC2100 DDR SDRAM Unbuffered SO-DIMM Reference Design Specification, Rev 1.0, it is
noted that pin 89 and pin 91 (CK2 and CK2#) of the SO-DIMM connector are reserved for x72 modules
or registered modules. By default, 852GME/852GMV/852PMdoes not drive SCK2, SCK2#, SCK5,
SCK5#. Therefore, it is important to make sure that the memory modules are not expected to use all
clock pairs.
6.6.

System Memory Compensation

See Section 12.5.4 for details.
6.7.

SMVREF Generation

See Section 12.5.3.1 for details.
6.8.

DDR Power Delivery

See Section 12.5.4 for details.
106
SO-DIMM1
SCK3,4,5
SMAB[1,2,4,5]
SCKE2,3; SCS#2,3
® ®
Intel 852GME, Intel 852GMV and Intel
System Memory Design Guidelines (DDR-SDRAM)
Example 2
SO-DIMM0 SO-DIMM1
SCK0,1,2 SCK3,4,5
SMAB[1,2,4,5] SMAA[1,2,4,5]
SCKE0,1; SCS#0,1 SCKE2,3; SCS#2,3
®
852PM Chipset Platforms Design Guide