Figure 4-9. Separate Links Vs Asymmetrical Loop Timing - Comtech EF Data SLM-7650 Installation And Operation Manual

SLM-7650 Satellite Modem
Theory of Operation
4.4.3.3.4 Asymmetrical Loop Timing (ASLT)
There are operational satellite links that have specific clocking requirements that include
the use of unequal data rates for transmit and receive. Asymmetrical loop timing (ASLT)
is an optional loop-timing mode that will allow for one timing standard in the circuit even
though the data rates are not equal. Compare the difference in clocking for the following
diagrams shown in Figure 4-9.

Figure 4-9. Separate Links vs Asymmetrical Loop Timing

The top example shows how most users would configure the clock as two separate
transmission links if the clock rates are not equal. No buffers are required and the setup
is very straightforward.
The bottom example shows how the ASLT allows for loop timing the transmission link
as if the data rates were equal. The timing standard at the master station is used for the
complete duplex asymmetrical satellite link. The synthesized phase lock loop circuit is
used at the slave end of the link to ensure that the ST output clock is phase locked to the
receive recovered satellite clock.
If ASLT is selected to be ON, the 'RX_Sat' clock is configured as the SCT-PLL-REF
source. There are, however, data rate restrictions and one of the following constraints
must be satisfied:
•
The receive data rate is equal to the transmit data rate.
•
The transmit data rate and the receive data rate are both integer multiples of 600 Hz.
•
The transmit data rate and the receive data rate are both integer multiples of 1 kHz.
Synthesized Phase
Lock Loop
4–32
Revision 4
MN/SLM7650.IOM